PI6C105 Datasheet, PDF (1/15 Pages) Pericom Semiconductor Corporation – Precision Clock Synthesizer for Mobile PCs

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Precision Clock Synthesizer
for Mobile PCs
Features
• Two copies of CPU clock with V_DD of 2.5V ±5%
• 100 MHz or 66 MHz operation
• Six copies PCI clock (synchronous with CPU clock) 3.3V
• One copy of Ref. clock @ 14.31818 MHz (3.3V_TTL)
• 48 MHz USB Clock, 24 MHz Super I/O clock
• I²C Serial Configuration Interface
• Spread Spectrum Modulation for CPUCLK, and PCICLK
• Low-cost 14.31818 MHz crystal oscillator input
• Power management control
• Isolated core V_DD, V_SS pins for noise reduction
• 28-pin SSOP and SOIC package (H)
Description
The PI6C105 is a high-speed, low-noise clock generator designed
to work with the PI6C18x family of clock buffers to meet all clock
needs for Mobile Intel Architecture platforms. CPU and chipset
clock frequencies of 66.6 MHz and 100 MHz are supported.
Split supplies of 3.3V and 2.5V are used. The 3.3V power supply
powers a portion of the I/O and the core. The 2.5V is used to power
the remaining outputs. 2.5V signaling follows JEDEC standard
8-X. Power sequencing of the 3.3V and 2.5V supplies is not
required.
An asynchronous PWR_DWN# signal may be used to power down
(or up) the system in an orderly manner.
Block Diagram
Pin Configuration
XTAL_IN
XTAL_OUT
Spread#
SEL100/66#
S_DATA
SCLK
REF
OSC
PLL1
I²C
PLL2
REF
CPU_STOP#
DIV
PCI_STOP#
2 _CPUCLK
[0:1]
5 _PCICLK
[1:5]
PCICLK_F
48 MHz
÷2
24 MHz
XTAL_IN 1
XTAL_OUT 2
V_{SSPCI 3}
PCICLK_F 4
PCICLK1 5
PCICLK2 6
PCICLK3 7
PCICLK4 8
V_DDPCI 9
PCICLK5 10
V_DDP2 11
48M/SPREAD# 12
V_SSP2 13
24M/SEL100/66# 14
28-Pin
H
28 V_SSREF
27 V_DDREF
26 REF
25 V_DDCPU
24 CPUCLK0
23 CPUCLK1
22 V_SSCPU
21 V_DDCORE
20 V_SSCORE
19 PCI_STOP#
18 CPU_STOP#
17 PWR_DWN#
16 S_DATA
15 SCLK
248
PS8316 03/15/99