PT7C4311 Datasheet, PDF (10/16 Pages) Pericom Semiconductor Corporation – Real-time Clock Module

PT7C4311
Real-time Clock Module (I²C Bus)
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 Year digits: Range from 00 to 99 and 00, 04, 08, … , 92 and 96 are counted as leap years.
Addr.
(hex)
04
05
06
Description
Dates (01-31)
(default)
Months (01-12)
(default)
Years (00-99)
(default)
D7
D6
D5
D4
D3
D2
D1
D0


D20
D10
D8
D4
D2
D1
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined



M10
M8
M4
M2
M1
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Y80
Y40
Y20
Y10
Y8
Y4
Y2
Y1
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Communication
1. I²C Bus Interface
a) Overview of I²C-BUS
The I²C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination
of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on.
Both the SCL and SDA signals are held at high level whenever communications are not being performed. The starting and
stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data
transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and on the receiving side the
data is captured while the SCL line is at high level. In either case, the data is transferred via the SCL line at a rate of one bit per
clock pulse. The I²C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a
chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its
slave address matches the slave address in the received data.
b) System Configuration
All ports connected to the I²C bus must be either open drain or open collector ports in order to enable AND connections to
multiple devices.
SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently, SCL and SDA are both held at high
level when the bus is released (when communication is not being performed).
Vcc
R_P
R_P
SDA
SCL
Master
MCU
Slave
RTC
Other Peripheral
Device
Note: When there is only one master, the MCU is ready for driving SCL to "H" and R _P of SCL may not required.
Fig.1 System configuration
2015-06-0002
PT0322-8
06/16/15
10