PI6ULS5V9627A Datasheet, PDF (1/10 Pages) Pericom Semiconductor Corporation – 4 Channel Level Translating Fast-Mode Plus I2C-bus/SMbus Repeater

PI6ULS5V9627A
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4 Channel Level Translating Fast-Mode Plus I²C-bus/SMbus Repeater
Features
 4 channel, bidirectional buffer isolates capacitance
and allows 540pF on either side of the device at 1
MHz and up to 4000 pF at lower speeds
 Voltage level translation from 0.6V to 5.5V and
from 2.2V to 5.5V
 Port A operating supply voltage range of 0.6V to
5.5V with normal levels( 0.4VCC(A) + 0.8 V ≤
VCC(B) )
 Port B operating supply voltage range of 2.2V to
5.5V with static offset level
 5V tolerant I²C-bus and enable pins
 0 Hz to 1 MHz clock frequency (the maximum
system operating frequency may be less than 1MHz
because of the delays added by the repeater)
 Active HIGH repeater enable input referenced to
VCC(B)
 Open-drain input/outputs
 Latching free operation
 Supports arbitration and clock stretching across the
repeater
 Accommodates Standard-mode, Fast-mode and
Fast-mode Plus I2C-bus devices, SMBus (standard
and high power mode), PMBus and multiple
masters
 Powered-off high-impedance I²C-bus pins
 ESD protection exceeds 8000V HBM per JESD22-
A114
 Package: TQFN-16L 4x4 and QSOP-16L
Pin Configuration
Description
The PI6ULS5V9627A is a CMOS integrated circuit
intended for Fast-mode Plus (Fm+) I²C-bus or SMBus
applications. It can provide level shifting between low
voltage (down to 0.6V) and higher voltage (2.2V to 5.5V)
in mixed-mode applications.
The PI6ULS5V9627A enables the system designer
to isolate two halves of a bus for both voltage and
capacitance, accommodating more I²C devices or longer
trace length. It also permits extension of the I²C-bus by
providing bidirectional buffering for both the data (SDA)
and the clock (SCL) lines, thus enabling two buses of
540 pF at 1 MHz or up to 4000 pF at lower speeds. The
SDA and SCL pins are overvoltage tolerant and are
high-impedance when the PI6ULS5V9627A is
unpowered.
The 2.2V to 5.5V bus port B drivers have the static
level offset, while the adjustable voltage bus port A
drivers eliminate the static offset voltage. This results in
a LOW on the port B translating into a nearly 0V LOW
on the port A which accommodates the smaller voltage
swings of lower voltage logic. The EN pin is referenced
to V_CC(B) and can also be used to turn the drivers on and
off under system control.
SCLA1 VCCA VCCB SCLB1
QSOP
SDAA1
GND
VCCA
SCLA2
TQFN
SDAB1
EN1
VCCB
SCLB2
2014-01-0009
QSOP-16L(Top View)
SDAA2 GND EN2 SDAB2
TQFN4x4-16L(Top View)
PT0485-1 02/11/14
1