PI6LC4830 Datasheet, PDF (1/11 Pages) Pericom Semiconductor Corporation – HiFlex Network Clock Generator

PI6LC4830
HiFlex^TM Network Clock Generator
Features
ÎÎ3.3V supply voltage
ÎÎ3 HCSL and 1 LVCMOS 100MHz outputs with OE/ function
ÎÎ1 LVCMOS 100/50MHz selectable
ÎÎ25MHz crystal or differential input
ÎÎLow 1ps RMS max integrated phase noise design
ÎÎPLL Bypass mode for test
ÎÎ32 lead 5x5mm TQFN package
Description
The PI6LC4830 is an LC VCO based low phase noise design
intended for the most demanding PCIe® 2.0 applications. Use
of the ultra-low noise LC VCO allows for much greater noise
margins than traditional solutions. This is ideal for noisy envi-
ronments.
Pin Configuration
PLL_Byps
REF_OUT_OE
QB_OE
QB_DIV2
VDD_PLL
IN+
IN-
VDD_REF_Out
32 31 30 29 28
1
27 26 25
24
2
23
3
22
4
GND
21
5
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
QA1+
QA1-
VDD_Out
QA2+
QA2-
GND
QA_CMOS
VDD_OutA_SE
Block Diagram
IN_SEL
OSC
IN+
IN-
12-0238
PLL_Byps
PLL
/R
1
REF_OUT_OE
REF_OUT
QA0:QA2
100MHz
HCSL Outputs
QA_CMOS
QA_OE
QB_CMOS
/2
QB_DIV2
QB_OE
PI6LC4830 Rev B
08/17/12