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PE9704_06 Datasheet, PDF (8/10 Pages) Peregrine Semiconductor Corp. – 3000 MHz UltraCMOS™ Integer-N PLL Rad Hard for Space Applications
Figure 4. Serial Interface Mode Timing Diagram
DATA
PE9704
Product Specification
E_WR
tEC
tCE
CLOCK
S_WR
tDSU
tDHLD
tClkH
tClkL
tCWR
tPW
tWRC
Enhancement Register
The functions of the enhancement register bits are shown below. All bits are active high. Operation is
undefined if more than one output is sent to DOUT.
Table 9. Enhancement Register Bit Functionality
Bit Function
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Reserved**
Reserved**
fp output
Power down
Counter load
MSEL output
fc output
PB
Description
Drives the M counter output onto the DOUT output.
Power down of all functions except programming interface.
Immediate and continuous load of counter programming.
Drives the internal dual modulus prescaler modulus select (MSEL) onto the DOUT output.
Drives the R counter output onto the DOUT output
Allows Fin to bypass the 10/11 prescaler
** Program to 0
Phase Detector Outputs
The phase detector is triggered by rising edges
from the main counter (fp) and the reference
counter (fc). It has two outputs, PD_U, and PD_D.
If the divided VCO leads the divided reference in
phase or frequency (fp leads fc), PD_D pulses
“low”. If the divided reference leads the divided
VCO in phase or frequency (fc leads fp), PD_U
pulses “low”. The width of either pulse is directly
proportional to phase offset between the two input
signals, fp and fc. The phase detector gain is
430 mV / radian.
PD_U and PD_D are designed to drive an active
loop filter which controls the VCO tune voltage.
PD_U pulses result in an increase in VCO
frequency and PD_D results in a decrease in VCO
frequency.
Software tools for designing the active loop filter
can be found at Peregrine’s web site:
www.psemi.com
Lock Detect Output
A lock detect signal is provided at pin LD, via the
pin CEXT (see Figure 1). CEXT is the logical “NAND”
of PD_U and PD_D waveforms, driven through a
series 2 kΩ resistor. Connecting CEXT to an
external shunt capacitor provides integration of
this signal.
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 8 of 10
Document No. 70-0083-03 │ UltraCMOS™ RFIC Solutions