PE9704_06 Datasheet, PDF (5/10 Pages) Peregrine Semiconductor Corp. – 3000 MHz UltraCMOS™ Integer-N PLL Rad Hard for Space Applications

PE9704
Product Specification
Table 6. AC Characteristics: V_DD = 3.0 V, -40° C < T_A < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Control Interface and Latches (see Figures 1and 3)
fClk
CLOCK Serial data clock frequency
(Note 1)
tClkH
CLOCK Serial clock HIGH time
30
tClkL
CLOCK Serial clock LOW time
30
tDSU
DATA set-up time after CLOCK rising edge
10
tDHLD
DATA hold time after CLOCK rising edge
10
tPW
S_WR pulse width
30
tCWR
CLOCK rising edge to S_WR rising edge.
30
tCE
CLOCK falling edge to E_WR transition
30
tWRC
S_WR falling edge to CLOCK rising edge.
30
tEC
E_WR transition to CLOCK rising edge
30
tMDO
MSEL data out delay after FIN rising edge
CL = 12 pf
Main Divider (Including Prescaler)
FIN
Operating frequency
500
PFin
Input level range
External AC coupling
-5
Main Divider (Prescaler Bypassed)
FIN
Operating frequency
50
PFin
Input level range
External AC coupling
-5
Reference Divider
FR
Operating frequency
(Note 3)
PFr
Reference input power (Note 2)
Single-ended input
-2
Phase Detector
fc
Comparison frequency
(Note 3)
Max
10
8
3000
5
300
5
100
20
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
dBm
MHz
dBm
MHz
dBm
MHz
Note 1: Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk
specification.
Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5Vp-p.
Note 3: Parameter is guaranteed through characterization only and is not tested.
Document No. 70-0083-03 │ www.psemi.com
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
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