PE9702 Datasheet, PDF (7/14 Pages) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Rad Hard Applications

PE9702
Advance Information
Table 6. AC Characteristics
V_DD = 3.0 V, -40° C < T_A < 85° C, unless otherwise specified
Symbol
Parameter
Control Interface and Latches (see Figures 3, 4, 5)
f_Clk
Serial data clock frequency
t_ClkH
Serial clock HIGH time
t_ClkL
Serial clock LOW time
t_DSU
Sdata set-up time after Sclk rising edge, D[7:0] set-up time
to M1_WR, M2_WR, A_WR, E_WR rising edge
t_DHLD
Sdata hold time after Sclk rising edge, D[7:0] hold time to
M1_WR, M2_WR, A_WR, E_WR rising edge
t_PW
S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width
t_CWR
Sclk rising edge to S_WR rising edge. S_WR, M1_WR,
M2_WR, A_WR falling edge to Hop_WR rising edge
t_CE
Sclk falling edge to E_WR transition
t_WRC
S_WR falling edge to Sclk rising edge. Hop_WR falling
edge to S_WR, M1_WR, M2_WR, A_WR rising edge
t_EC
E_WR transition to Sclk rising edge
t_MDO
MSEL data out delay after Fin rising edge
Main Divider (Including Prescaler)
F_in
Operating frequency
P_Fin
Input level range
Main Divider (Prescaler Bypassed)
F_in
Operating frequency
P_Fin
Input level range
Reference Divider
f_r
Operating frequency
P_fr
Reference input power (Note 2)
Phase Detector
f_c
Comparison frequency
Conditions
(Note 1)
C_L = 12 pf
External AC coupling
External AC coupling
(Note 3)
Single-ended input
(Note 3)
Min
Max
Units
10
MHz
30
ns
30
ns
10
ns
10
ns
30
ns
30
ns
30
ns
30
ns
30
ns
8
ns
500
3000
MHz
-5
5
dBm
50
300
MHz
-5
5
dBm
100
MHz
-2
dBm
20
MHz
Note 1: Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk
specification.
Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5V_p-p.
Note 3: Parameter is guaranteed through characterization only and is not tested.
PEREGRINE SEMICONDUCTOR CORP.  | http://www.peregrine-semi.com
Copyright  Peregrine Semiconductor Corp. 2003
Page 7 of 15