PE9702 Datasheet, PDF (12/14 Pages) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Rad Hard Applications

Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 9. Enhancement Register Bit Functionality
Bit Function
Description
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Reserved**
Reserved**
Reserved**
Power down
Counter load
Bit 5
MSEL output
Bit 6 Prescaler output
Bit 7
f_p, f_c OE
** Program to 0
Power down of all functions except programming interface.
Immediate and continuous load of counter programming as directed by the Bmode and
Smode inputs.
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Drives the raw internal prescaler output (fmain) onto the Dout output.
f_p, f_c outputs disabled.
PE9702
Advance Information
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (f_p) and the reference
counter (f_c). It has two outputs, namely PD_U, and
PD_D. If the divided VCO leads the divided
reference in phase or frequency (f_p leads f_c), PD_D
pulses “low”. If the divided reference leads the
divided VCO in phase or frequency (f_r leads f_p),
PD_U pulses “low”. The width of either pulse is
directly proportional to phase offset between the
two input signals, f_p and f_c. The phase detector gain
is 430 mV / radian.
PD_U and PD_D are designed to drive an active
loop filter which controls the VCO tune voltage.
PD_U pulses result in an increase in VCO
frequency and PD_D results in a decrease in VCO
frequency.
A lock detect output, LD is also provided, via the pin
Cext. Cext is the logical “NAND” of PD_U and
PD_D waveforms, which is driven through a series
2k ohm resistor. Connecting Cext to an external
shunt capacitor provides integration. Cext also
drives the input of an internal inverting comparator
with an open drain output. Thus LD is an “AND”
function of PD_U and PD_D. See Figure 3 for a
schematic of this circuit.
Copyright  Peregrine Semiconductor Corp. 2003
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