PE3340 Datasheet, PDF (7/12 Pages) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Low Phase Noise Applications

Main Counter Chain
Normal Operating Mode
Setting the Pre_en control bit “low” enables the
÷10/11 prescaler. The main counter chain then
divides the RF input frequency (F_in) by an integer
derived from the values in the “M” and “A” counters.
In this mode, the output from the main counter
chain (f_p) is related to the VCO frequency (F_in) by
the following equation:
f_p = F_in / [10 x (M + 1) + A]
(1)
where A ≤ M + 1, 1 ≤ M ≤ 511
When the loop is locked, F_in is related to the
reference frequency (f_r) by the following equation:
F_in = [10 x (M + 1) + A] x (f_r / (R+1))
(2)
where A ≤ M + 1, 1 ≤ M ≤ 511
A consequence of the upper limit on A is that F_in
must be greater than or equal to 90 x (f_r / (R+1)) to
obtain contiguous channels. The A counter can
accept values as high as 15, but in typical operation
it will cycle from 0 to 9 between increments in M.
Programming the M counter with the minimum
allowed value of “1” will result in a minimum M
counter divide ratio of “2”.
Prescaler Bypass Mode
Setting the frequency control register bit Pre_en
“high” allows F_in to bypass the ÷10/11 prescaler. In
this mode, the prescaler and A counter are powered
down, and the input VCO frequency is divided by
the M counter directly. The following equation
relates F_in to the reference frequency f_r:
F_in = (M + 1) x (f_r / (R+1))
(3)
where 1 ≤ M ≤ 511
Reference Counter
The reference counter chain divides the reference
frequency f_r down to the phase detector comparison
frequency f_c.
The output frequency of the 6-bit R Counter is
related to the reference frequency by the following
equation:
f_c = f_r / (R + 1)
(4)
where 0 ≤ R ≤ 63
Note that programming R with “0” will pass the
reference frequency (f_r) directly to the phase
detector.
Register Programming
Serial Interface Mode
While the E_WR input is “low” and the S_WR input
is “low”, serial input data (Sdata input), B₀ to B₁₉,
are clocked serially into the primary register on the
rising edge of Sclk, MSB (B₀) first. The contents
from the primary register are transferred into the
secondary register on the rising edge of either
S_WR according to the timing diagrams shown in
Figure 4. Data are transferred to the counters as
shown in Table 7 on page 9.
The double buffering provided by the primary and
secondary registers allows for “ping-pong” counter
control using the FSELS input. When FSELS is
“high”, the primary register contents set the counter
inputs. When FSELS is “low”, the secondary
register contents are utilized.
While the E_WR input is “high” and the S_WR input
is “low”, serial input data (Sdata input), B₀ to B₇, are
clocked serially into the enhancement register on
the rising edge of Sclk, MSB (B₀) first. The
enhancement register is double buffered to prevent
inadvertent control changes during serial loading,
with buffer capture of the serially entered data
performed on the falling edge of E_WR according to
the timing diagram shown in Figure 4. After the
falling edge of E_WR, the data provide control bits
as shown in Table 8 on page 9 will have their bit
functionality enabled by asserting the Enh input
“low”.
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