PE3511 Datasheet, PDF (6/9 Pages) Peregrine Semiconductor Corp. – 1500 MHz Low Power UltraCMOS™ Divide-by-2 Prescaler

Evaluation Kit
Evaluation Kit Operation
The SC-70 Prescaler Evaluation Board was
designed to help customers evaluate the PE3511
divide-by-2 prescaler. On this board, the device
input (pin 3) is connected to connector J1 through a
50 Ω transmission line. A series capacitor (C1)
provides the necessary DC block for the device
input. A value of 100 pF was used for this board
layout; other applications may require a different
value.
The device output (pin 6) is connected to J3 through
a 50 Ω transmission line. A series capacitor (C5)
provides the necessary DC block for the device
output. This capacitor value must be chosen to have
a low impedance at the desired output frequency of
the device. A value of 100 pF was chosen for the
evaluation board. At both input and output, select a
capacitor value that offers low series reactance while
ensuring that any parasitic resonances are well
above the operating bandwidth.
The board is constructed of a two-layer FR4 material
with a total thickness of 0.031”. The bottom layer
provides ground for the RF transmission lines. The
transmission lines were designed using a coplanar
waveguide above ground plane model with trace
width of 0.030”, trace gaps of 0.007”, dielectric
thickness of 0.028”, metal thickness of 0.0014”, and
ε_r of 4.4. Note that the predominate mode of these
transmission lines is coplanar waveguide. Liberal
numbers of plated through holes unite the top and
PE3511
Product Specification
bottom ground areas for best performance.
J6 provides DC power to the device via pin 4. Two
decoupling capacitors (100 pF, 1000 pF) are
included on this trace. It is the customer’s
responsibility to determine proper supply decoupling
for their design application.
Applications Support
If you have a problem with your evaluation kit or if
you have applications questions call [phone]
and ask for applications support. You may also con-
tact us by fax or e-mail:
Fax: [phone]
E-Mail: [e-mail]
Figure 9. Evaluation Board Layouts
Peregrine Specification 101/0110
Figure 10. Evaluation Board Schematic
Peregrine Specification 102/0189
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 9
Document No. 70-0106-06 │ UltraCMOS™ RFIC Solutions