PE3511 Datasheet, PDF (3/9 Pages) Peregrine Semiconductor Corp. – 1500 MHz Low Power UltraCMOS™ Divide-by-2 Prescaler

PE3511
Product Specification
Figure 3. Pin Configuration (Top View)
pin 1
NC ¹
GND ²
IN ³
6 _OUT
5 _GND
SC-70
4
V_DD
Table 5. Pin Descriptions
Pin
Pin
No. Name
Description
1
N/C No Connect. This pin should be left open.
Ground pin. Ground pattern on the board
2
GND should be as wide as possible to reduce
ground impedance.
3
IN
Input signal pin. DC blocking capacitor
required (100 pF typical).
4
V_DD Power supply pin. Bypassing is required.
5
GND Ground pin.
6
OUT
Divided frequency output pin. DC blocking
capacitor required (100 pF typical).
Table 6. Absolute Maximum Ratings
Symbol Parameter/Conditions Min Max Units
V_DD
Supply voltage
4.0
V
Pin
Input Power
13
dBm
T_ST
Storage temperature range -65 150
°C
T_OP
Operating temperature
range
-40 85
°C
VESD
ESD voltage (Human Body
Model)
2000
V
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 6.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Device Functional Considerations
The PE3511 divides an input signal, up to a
frequency of 1500 MHz, by a factor of two thereby
producing an output frequency at half the input
frequency. To work properly with low impedance,
ground referenced interfaces, the input and output
signals (pins 3 & 6) must be AC coupled via an
external capacitor, as shown in the test circuit in
Figure 4.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance. See Figure 9 for a layout example.
Document No. 70-0106-06 │ www.psemi.com
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
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