PE94302_07 Datasheet, PDF (3/6 Pages) Peregrine Semiconductor Corp. – 50 ohm RF Digital Step Attenuator For Rad-Hard Space Applications 6-bit, 31.5 dB, DC - 4.0 GHz

PE94302
Advance Information
Programming Options
Parallel/Serial Selection
Either a parallel or serial interface can be used to
control the PE94302. The P/S bit provides this
selection, with P/S=LOW selecting the parallel
interface and P/S=HIGH selecting the serial
interface.
Parallel Mode Interface
The parallel interface consists of six CMOS-
compatible control lines that select the desired
attenuation state, as shown in Table 5.
The parallel interface timing requirements are
defined by Figure 5 (Parallel Interface Timing
Diagram), Table 8 (Parallel Interface AC
Characteristics), and switching speed (Table 1).
For latched parallel programming the Latch Enable
(LE) should be held LOW while changing attenuation
state control values, then pulse LE HIGH to LOW
(per Figure 5) to latch new attenuation state into
device.
For direct parallel programming, the Latch Enable
(LE) should be either pulled high or floated (see
Table 2, note 2). Changing attenuation state control
values will change device state to new attenuation.
Direct Mode is ideal for manual control of the device
(using hardwire, switches, or jumpers).
Table 5. Truth Table
P/S C16 C8 C4 C2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
1
1
1
C1
C0.5
Attenuation
State
0
0 Reference Loss
0
1
0.5 dB
1
0
1 dB
0
0
2 dB
0
0
4 dB
0
0
8 dB
0
0
16 dB
1
1
31.5 dB
Note: Not all 64 possible combinations of C0.5-C16 are shown in table
Serial Interface
The serial interface is a 6-bit serial-in, parallel-out
shift register buffered by a transparent latch. It is
controlled by three CMOS-compatible signals: Data,
Clock, and Latch Enable (LE). The Data and Clock
inputs allow data to be serially entered into the shift
register, a process that is independent of the state of
the LE input.
The LE input controls the latch. When LE is HIGH,
the latch is transparent and the contents of the serial
shift register control the attenuator. When LE is
brought LOW, data in the shift register is latched.
The shift register should be loaded while LE is held
LOW to prevent the attenuator value from changing
as data is entered. The LE input should then be
toggled HIGH and brought LOW again, latching the
new data. The timing for this operation is defined by
Figure 4 (Serial Interface Timing Diagram) and Table
7 (Serial Interface AC Characteristics).
Document No. 70/0186-02 │ www.psemi.com
©2005-2007 Peregrine Semiconductor Corp. All rights reserved.
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