PE9304 Datasheet, PDF (3/6 Pages) Peregrine Semiconductor Corp. – 1- 7 GHz Low Power CMOS Divide-by-2 Prescaler

PE9304
Product Specification
Evaluation Kit Operation
The Ceramic SOIC Prescaler Evaluation Board was
designed to help customers evaluate the PE9304
divide-by-2 prescaler. On this board, the device
input (pin 2) is connected to the SMA connector J1
through a 50 Ω transmission line. A series capacitor
(C3) provides the necessary DC block for the device
input. A value of 2.2 pF was used for the evaluation
board; other applications may require a different
value.
The device output (pin 7) is connected to SMA
connector J3 through a 50 Ω transmission line. A
series capacitor (C1) provides the necessary DC
block for the device output. This capacitor value
must be chosen to have low impedance at the
desired output frequency of the device. A value of
2.2 pF was chosen for the evaluation board.
J2 provides DC power to the device via pin 1. Two
decoupling capacitors (C2=1000 pF, C10=100 pF)
are included on this trace. It is the responsibility of
the customer to determine proper supply decoupling
for their design application.
The board is constructed using 4 layers. The top
and bottom layers are comprised of Rogers low loss
4350 material having a core thickness of 0.010”;
while the internal layers are comprised of FR-4. The
overall board thickness is 0.062”.
Figure 4. Evaluation Board Layout
Peregrine specification 101/0034
Applications Support
If you have a problem with your evaluation kit or if
you have applications questions, please contact
applications support:
E-Mail: [e-mail] (fastest response)
Phone: [phone]
Figure 5. Evaluation Board Schematic
Peregrine specification 102/0223
Document No. 70-0152-02 │ www.psemi.com
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
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