PE3342 Datasheet, PDF (12/17 Pages) Peregrine Semiconductor Corp. – 2.7 GHz Integer-N PLL with Field-Programmable EEPROM Features

PE3342
Product Specification
Figure 8. Details of EE register contents loaded from EEPROM and then shifted out Serially through
Dout pin - The procedure is performed twice.
EELoa ^3V
d
0V
3V
EESel
0V
S_WR
0V
3V
E_WR
0V
3V
Data
0V
3V
Clock
0V
Dout _3V
(example)
0 1010011111000111001
0V
Enhancement
Register
Programming
EE Register
load from
EEPROM
EE Register
shifted out
through Dout
Rough time scale
20 us
Note: ENH/ ( Pin 3 in TSSOP or Pin 20 in QFN) is at low (0) for this process.
In Figure 8, the first step is to program
Enhancement Register to set Bit 1 high (“1”) to
access EE Register Output Bit Function.
Subsequent action, which includes 19 Clock
pulses, allows the existing EE Register contents to
be shifted out the Dout pin and the EEPROM
contents are loaded to the EE Register. Since the
initial data existing in the EE Register could be
anything, the data must be flushed out before
clocking the contents of the EEPROM register out.
After the same procedure is duplicated, the Dout
output is the EEPROM contents. Note that only
19 Clock pulses are enough for the 20-bit EE
Register because the first bit data is already
present at Dout pin. Also ENH/ (Pin 3 in TSSOP
or Pin 20 in QFN) is set to low (“0”) to access the
Enhancement mode.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 12 of 17
Document No. 70-0091-03 │ UltraCMOS™ RFIC Solutions