PE3342 Datasheet, PDF (11/17 Pages) Peregrine Semiconductor Corp. – 2.7 GHz Integer-N PLL with Field-Programmable EEPROM Features

PE3342
Product Specification
Gross EEPROM Programming Timing Grid
Figure 7 shows a gross PE3342 EEPROM
programming timing grid although each individual
step has been described thoroughly in previous
sections. It starts with EE Register load, and then
together with other parameters a Vpp_ERASE
negative pulse is applied to Vpp pin to erase the
EEPROM contents and followed by a Vpp_WRITE
pulse for EEPROM write cycle. The separation
between the Vpp_ERASE and Vpp_WRITE pulse
has to be at least 100 ms if mechanical relays are
used to avoid both being on at the same time.
After EE programming, the contents of the
EEPROM cells can be verified by setting
Enhancement Register Bit 1. A procedure shown
in Figure 8 is applied twice. The first time is to
load the EE Register from EEPROM and the
second time is to shift out the EE Register
contents through Dout pin.
Figure 7. Gross PE3342 EEPROM Programming Timing Grid
EELoa ^3V
d
0V
3V
EESel
0V
3V
S_WR
0V
3V
>=100 ms
E_WR
0V
3V
Data
0V
3V
Clock
0V
3V
Dout
0V
CHANNEL
CODE
ENH code set's
Dout mux to EE
0V
Vpp_ERASE
-8.5V
12.5V
Vpp_WRITE
0V
25 ms
25 ms
EE Register
load
EE PROM
Erase
EE PROM
W rite
Rough time scale
40 ms
Note: ENH/ ( Pin 3 in TSSOP or Pin 20 in QFN) is at
low (0) for this process.
The final set
of Dout is
EEPROM
content
EE Register
load from
EEPROM
EE Register
shifted out
through Dout
Document No. 70-0091-03 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
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