MN38663S Datasheet, PDF (5/6 Pages) Panasonic Semiconductor – NTSC-Compatible CCD Video Signal Delay Element

CCD Delay Line Series
Application Circuit Example
0.1µF
+ 4.4V
– 10m
0.1µF
0.1µF
4.4V or GND
MN38663S
0.01µF
0.01µF
Bias circuit
Clamp
circuit
Mode switch
Booster
circuit
Voltage
generator
Signal
input _{VINVC 6}
L
–+
0.47µF
Signal
H
input _{VINC1 4}
H
–+
0.47µF
L
Signal
input _{VINVY 15}
L
–+
0.47µF
Signal
H
input _{VINC2 13}
H
–+
0.47µF
Clock
L
input _{XIV 20} L
1000pF
Clock
input _{XIC 1}
1000pF
H
Waveform
amplifier
adjustment
block
LH
Phase
comparator
Charge
input
block
78.5-stage
analog
shift
register
Charge
input
block
3-stage
analog
shift
register
Charge
input
block
78.5-stage
analog
shift
register
Charge
input
block
3-stage
analog
shift
register
H
L
H
602-stage
analog
shift
register
L
H
L
H
602-stage
analog
shift
register
L
H
Charge
detector
Charge
detector
1/3rd
L
frequency
divider
Waveform
adjustment
block
ø1 driver
VCO
Timing
adjustment
L
H
ø2 driver
Voltage
generator
Resampling
output amplifier
Resampling
output amplifier
øS driver
øR driver
øSH driver
Substrate
bias generator
8 ^VO1C
Signal
output
(1C)
11 VO2Y
Signal
output
(2Y)
0.01µF
820Ω
1000pF
Note: If the capacitor attached to pin 18 has a polarity, attach the negative pole to pin 18.
0.01µF
5