MN89201 Datasheet, PDF (4/11 Pages) Panasonic Semiconductor – VGA-NTSC Scan Converter

MN89201
Pin Descriptions
Pin No.
Symbol
I/O
3
AEN
I
4
XRD
I
5
XWE
I
6
REGLIN
I
7 to 10
RA[3:0]
I
11 to 14
DB[7:0]
I
17 to 20
23
RESET
I
24 ,25 MODSET[1:0]
I
For Information Equipment
Function Description
Chip select signal
"L" level: Register access enabled
"H" level: Register access disabled
Read control signal
"L" level: Read enabled
Write control signal
"L" level: Write enabled
Register address mode specification
"H" level: Obtain register address from RA[3:0]
"L" level: Obtain register address from address register
In the latter case, the address of the parameter/mode register are
specified by the address register .
Address register: 0H (4-bit decode)
Data register: 1H (4-bit decode)
Register address specification
Host data bus
MN89201 reset signal
Active "H"
This signal initializes internal registers to their default values and
resets internal synchronization counters.
Synchronization mode specification pins
These specify the RDCLK synchronization mode for output signals
to the NTSC encoder
(1:0)
0 0: Use an external VCO clock signal synchronized with the VGA
clock signal for RDCLK. The XH, XVSYNC, XBLANK, and
XENRST signals are generated inside the MN89201 and are
outputted. (synchronous)
0 1: Use an external oscillator clock signal not synchronized with
the VGA clock signal for RDCLK. The XH and XVSYNC
signals are retimed versions of the VGA H and VSYNC
signals. (asynchronous)
The other outputs use the VGA DOTCLK signal.
1 0: Use the VGA DOTCLK signal for RDCLK. The YCrCb data,
XVSYNC, XBLANK, and XENRST signals all are dealt in
the VGA clock. An external oscillator is not necessary.
(synchronous)