EXBV8V472JV_1 Datasheet, PDF (4/5 Pages) Panasonic Semiconductor – Chip Resistor Array

q Punched (Paper) Taping Reel
Chip Resistor Array
q Punched (Paper) Taping
Type
Dimensions
(mm)
14V, 2HV
24V, 28V
V4V, 34V
V8V, 38V
Type
Dimensions ^{14V, 2HV}
(mm) ^{24V, 28V}
V4V, 34V
V8V, 38V
fA
180.0_Ð03.0
W
9.0^±1.0
fB
60 min.
fC
13.0^±1.0
T
11.4^±2.0
q Embossed Taping Reel
Type A
14V 0.70^±0.05
24V
28V
Dimensions
(mm)
V4V
34V
1.20 ^±0.05
1.95 ^±0.15
V8V _2.00±0.15
38V
2HV 1.90^±0.15
B
0.90 ^±0.05
1.20 ^±0.05
2.20^±0.10
1.95 ^±0.20
3.60 ^±0.20
4.10 ^±0.15
W
8.00 ^±0.20
F
3.50 ^±0.05
E
1.75 ^±0.10
Type P1
14V
24V 2.00^±0.10
28V
Dimensions
(mm)
V4V
34V
V8V 4.00^±0.10
38V
2HV
P2
2.00 ^±0.05
P0
4.00 ^±0.10
fD0
1.50
+0.10
0
T
0.45 ^±0.05
0.84 ^±0.05
0.64 ^±0.05
0.84 ^±0.05
0.64 ^±0.05
q Embossed Taping
Dimensions Type
(mm) S8V
fA
180.0
0
Ð3.0
fB
60 min.
fC
13.0^±1.0
Dimensions ^{Type A}
B
W
F
E
P0
(mm) S8V 2.80^±0.20 5.70^±0.20 12.00^±0.30 5.50^±0.05 1.75^±0.10 4.00^±0.10
Dimensions Type
(mm) S8V
W
13.0^±1.0
T
15.4^±2.0
Dimensions Type P₁
P₂
fD₀
t₂
fD₁
(mm)
S8V 4.00^±0.10
2.00 ^±0.05
1.50
+0.10
0
1.6 max.
1.50
+0.10
0
s Land pattern design
Recommendable land pattern design for Network chip is as shown below figure.
Type
a
14V
0.3
Dimensions
(Not to scale)
Unit (mm)
b
c
p
f
0.3
0.3
0.50
0.9
24V
0.5 0.35 to 0.40 0.35 to 0.40 0.65 1.4 to 1.5
28V
0.4
0.525
0.25
0.50
1.4
V4V,V8V 0.7 to 0.9 0.4 to 0.45 0.4 to 0.45 0.80 2 to 2.4
34V,38V 0.7 to 0.9 0.4 to 0.5 0.4 to 0.5 0.80 2.2 to 2.6
S8V 1 to 1.2 0.5 to 0.75 0.5 to 0.75 1.27 3.2 to 3.8
2HV
1
0.425
0.25
0.50
2