MN3883S Datasheet, PDF (3/4 Pages) Panasonic Semiconductor – Full Multi-PAL-Compatible CCD Video Signal Delay Element

CCD Delay Line Series
Application Circuit Example
MN3883S
10µF
–+
0.1µF
(0.01µF)
Bias circuit
VINC ^{16 P Charge}
input
(0.01µF)
block
443N _Charge
input
block
N _Charge
input
block
øS driver
CCD
8 stages
+
CCD
108 stages
+
CCD
451 stages
Charge detec-
tion block
2
Resampling
output amplifier
VOC
CCD
3.5 stages
CCD
3 stages
ø1 driver
ø2 driver
øR driver
øSH driver
øSH driver
Timing adjustment
N
443N P
XI 13 _{Waveform amplifier}
adjustment block
1000pF
1/2nd frequency
doubler
Timing adjustment
øS driver
ø1 driver
ø2 driver
øR driver
øSH driver
øSH driver
Clamp circuit
P _Charge
input
block
VINY ^{9 443N} Charge
–+
0.47µF
input
block
N Charge
input
block
CCD
7.5 stages
+
CCD
108 stages
+
CCD
451 stages
CCD
3.5 stages
CCD
3 stages
Mode
selection
circuit
Charge detec-
tion block
Resampling ^{7 VOY}
output amplifier
(0.01µF)
Three input levels:
H: NTSC
M: 4.43 NTSC
L: PAL
(0.01µF)
Note: When an electlytic capacitor is attached to pin 5, connect the negative pole to pin 5.
3