MN3883S Datasheet, PDF (2/4 Pages) Panasonic Semiconductor – Full Multi-PAL-Compatible CCD Video Signal Delay Element

MN3883S
Block Diagram
CCD Delay Line Series
Bias circuit
VINC
16 ^P Charge
input
block
443N _Charge
input
block
N Charge
input
block
CCD
8 stages
+
CCD
108 stages
+
CCD
451 stages
CCD
3.5 stages
CCD
3 stages
Charge
detection
block
øS driver
ø1 driver
ø2 driver
øR driver
Resampling
VOC
output amplifier ²
øSH driver
øSH driver
Timing adjustment
N
443N ^P
XI ^{13 Waveform amplifier}
adjustment block
1/2nd frequency
doubler
Timing adjustment
øS driver
ø1 driver
ø2 driver
øR driver
øSH driver
øSH driver
Clamp circuit
VINY
P _Charge
input
block
9 ^443N Charge
input
block
N Charge
input
block
CCD
7.5 stages
+
CCD
108 stages
+
CCD
451 stages
CCD
3.5 stages
CCD
3 stages
Mode
selection
circuit
Charge detec- _Resampling
7
tion block
output amplifier ^VOY
Three input levels: H: NTSC
M: 4.43 NTSC
L: PAL
2