EZANPE101M Datasheet, PDF (3/5 Pages) Panasonic Semiconductor – Chip Capacitor Networks

■ Packaging Methods (Taping)
● Standard Quantity
Type
Kind of Taping
EZANP
Embossed Carrier Taping
Pitch (P1)
4 mm
Chip Capacitor Networks
Quantity
4000 pcs./reel
● Embossed Carrier Taping
t1
Compartment
Sprocket hole
fD0
A
● Taping Reel
T
fC
t2
fD1
Chip component
P1 P2 P0 Tape running direction
A
B
W
F
E
P0
Dimensions
(mm)
3.50^±0.20
6.80^±0.20
12.00^±0.30
5.50^±0.20
1.75^±0.20
4.00^±0.10
P1
P2
fD0
t1
t2
fD₁
Dimensions
(mm)
4.00^±0.10
2.00^±0.05
1.50_−+00.10
0.25^±0.05
1.30^±0.20
1.50_−+00.10
fA
W
Dimensions
(mm)
Dimensions
(mm)
fA
180.0^+−03.0
fB
60 min.
fC
13.0^±1.0
W
13.0^±1.0
T
15.4^±2.0
■ Recommended Land Pattern Design
P
b
(0.20)
: Land pattern
a
b
c
d
Dimensions
(mm)
2.2 to 2.4
0.4 to 0.6
5.7 to 5.9
0.4 to 0.8
c
f
g
P
g
Dimensions
(mm)
4.2 to 4.6
7.5 to 7.9
1.27
Design and specifications are each subject to change without notice. Ask factory for the current technical specifications before purchase and/or use.
Should a safety concern arise regarding this product, please be sure to contact us immediately.
Feb. 2006