XN1872 Datasheet, PDF (1/2 Pages) Panasonic Semiconductor – Silicon N-channel . Enhancement MOS FET

Composite Transistors
XN1872
Silicon N-channel • Enhancement MOS FET
For switching
s ^Features
q Two elements incorporated into one package.
(Source-coupled FETs)
q Reduction of the mounting area and assembly cost by one half.
0.65±0.15
5
4
3
2.8
+0.2
-0.3
1.5
+0.25
-0.05
Unit: mm
0.65±0.15
1
2
s ^{Basic Part Number of Element}
q 2SK621 × 2 elements
0.1 to 0.3
0.4±0.2
s ^{Absolute Maximum Ratings (Ta=25˚C)}
Parameter
Symbol
Ratings
Unit
Drain to source voltage
V_DSS
50
V
Rating _{Gate to source voltage}
of
V_GSO
8
V
element _{Drain current}
I_D
100
mA
I_DM
200
mA
Total power dissipation
P_T
300
mW
Overall Channel temperature
T_ch
150
˚C
Storage temperature
T_stg
–55 to +150
˚C
1 : Drain (Tr1)
2 : Drain (Tr2)
3 : Gate (Tr2)
4 : Source
5 : Gate (Tr1)
EIAJ : SC–74A
Mini Type Pakage (5–pin)
Marking Symbol: 5U
Internal Connection
FET 1
5
1
4
3
s ^{Electrical Characteristics (Ta=25˚C)}
Parameter
Symbol
Conditions
min
Drain to source voltage
V_DSS
Drain current
I_DSS
Gate cutoff current
I_GSS
Gate threshold voltage
V_th
Drain resistance
R_DS(on)
Forward transfer admittance
| Y_fs |
Output voltage high level
V_OH
Output voltage low level
Input resistance
Turn-on time
Turn-off time
V_OL
R₁+R_2*1
t_on*2
t_off*2
Common source short-circuit input capacitance C_iss
*1 _{Pulse measurement}
*2 _{Resistance ratio R1/R2 = 1/50}
I_D = 100µA, V_GS = 0
50
V_DS = 10V, V_GS = 0
V_GS = 8V, V_DS = 0
40
I_D = 100µA, V_DS = V_GS
1.5
I_D = 20mA, V_GS = 5V
I_D = 20mA, V_DS = 5V, f = 1kHz
20
V_DS = 5V, V_GS = 1V, R_L = 200Ω
4.5
V_DS = 5V, V_GS = 5V, R_L = 200Ω
100
V_DD = 5V, V_GS = 0 to 5V, R_L = 200Ω
V_DD = 5V, V_GS = 5 to 0V, R_L = 200Ω
V_DS = 5V, V_GS = 0, f = 1MHz
2
FET 2
typ max Unit
V
10
µA
80
µA
3.5
V
50
Ω
30
mS
V
1.0
V
200
kΩ
1.0
µs
1.0
µs
9
15
pF
1