MN3880S Datasheet, PDF (1/6 Pages) Panasonic Semiconductor – NTSC CCD Video Signal Delay Element

CCD Delay Line Series
MN3880S
NTSC CCD Video Signal Delay Element
Overview
The MN3880S is a CCD signal delay element for video
signal processing applications.
It contains such components as a shift register clock
driver, charge I/O blocks, two CCD delay elements, a
clamp bias circuit, resampling output amplifiers, and
booster circuits.
The MN3880S samples the input using the supplied
clock signal with a frequency of 7.15909 MHz, twice the
NTSC color signal subcarrier frequency, and after add-
ing in the attached filter delay, produces independent de-
lays of 1 H (the horizontal scan period) each for the two
lines.
Features
Single 4.9 V power supply
Single chip combining luminance signal delay
element and delay element for chrominance signal
after passing through a low pass filter
Applications
VCRs
Pin Assignment
VBIASC
1
VOC
2
N.C.
3
V_DD
4
–V_BB
5
N.C.
6
VOY
7
VBIASY
8
16
VINC
15
N.C.
14
N.C.
13
X1
12
V_SS
11
N.C.
10
N.C.
9
VINY
(TOP VIEW)
SOP016-P-0225
1