MN38662S Datasheet, PDF (1/4 Pages) Panasonic Semiconductor – NTSC-Compatible CCD Video Signal Delay Element

CCD Delay Line Series
MN38662S
NTSC-Compatible CCD Video Signal Delay Element
Overview
The MN38662S is a CCD signal delay element for video
signal processing applications.
It contains such components as a threefold-frequency
circuit, a shift register clock driver, charge I/O blocks,
two CCD analog shift registers switchable between 681
and 605 stages, a clamp bias circuit, resampling output
amplifiers, and booster circuits.
When the switch input is "L" level, the MN38662S
samples the input using the supplied clock signal with a
frequency of three times the NTSC color signal subcarrier
frequency (3.579545 MHz) and, after adding in the at-
tached filter delay, produces independent delays of 1 H
(the horizontal scan period) each for the two lines. When
the switch input is "H" level, the MN38662S disables the
threefold-frequency circuit and samples the input with
the image sensor drive frequency (9.53496 MHz or
9.545454 MHz) for the camera's 510 horizontal pixels
and, after adding in the attached filter delay, produces
independent delays of 1 H (the horizontal scan period)
each for the two lines.
Features
Single 4.8 V power supply
Choice of camera and VCR modes, so that both the
camera and VCR portions of a video camera with 510
horizontal pixels can use the same MN38662S for sig-
nal processing
Applications
Video cameras
Pin Assignment
XIC
1
V_SS3
2
V_DD3
3
VINC1
4
N.C.
5
VINVC
6
VGC1
7
VO1C
8
V_DD1
9
V_SS1
10
20
XIV
PCOUT
19
&
VCOIN
18
–V_BB
17
V_SS2
16
V_DD2
15
VINVY
14
SW
13
VINC2
12
VGC2
11
VO2Y
( TOP VIEW )
SOP020-P-0300
1