MN101D07G Datasheet, PDF (1/5 Pages) Panasonic Semiconductor – MN101D07G

MN101D07G, MN101D07H
Type
Internal ROM type
ROM (byte)
RAM (byte)
Package (Lead-free)
Minimum Instruction
Execution Time
MN101D07G
MN101D07H
Mask ROM
128K
160K
4K
5K
LQFP112-P-2020
[With main clock operated]
0.1397 µs (at 4.0 V to 5.5 V, 14.32 MHz)
71.5 µs (at 3.0 V to 5.5 V, 14.32 MHz internal frequency di Vision)
[When sub-clock operated]
61 µs (at 2.2 V to 5.5 V, 32.768 kHz)
MN101DF07Z
FLASH
224K
6K
0.1397 µs (at 4.0 V to 5.5 V,14.32 MHz)
71.5 µs (at 3.0 V to 5.5 V, 14.32 MHz
internal frequency di Vision)
61 µs (at 2.5 V to 5.5 V, 32.768 kHz)
 Interrupts
RESET, Runaway, External 0 to 4, key input (P50 to P54), Timer 0 to 4, Timer 6, Timer 7, Capstan FG, Control, HSW,
Cylinder(Drum) FG, Servo V-sync, Synchronous output, OSD, XDS, Serial 0 to 2, A/D (common with PWM 4 reference frequency),
OSD V-sync
 Timer Counter
Timer counter 0 : 16-bit × 1
(timer function, clock function [max. 2 s or max. 36 h at cascade-connecting with timer 6])
Clock source................ 1/2, (1/4,) 1/8, (1/16) of system clock frequency; overflow of timer counter 6; 1/512 of XI oscillation
clock or OSC oscillation clock frequency
Interrupt source ........... overflow of timer counter 0
Timer counter 1 : 16-bit × 1 (timer function, linear timer counter function)
Clock source................ 1/2, (1/4,) 1/8, (1/16) of system clock frequency; CTL signal
Interrupt source ........... overflow of timer counter 1
Timer counter 2 : 16-bit × 1
(timer function, input capture
(DCTL specified edge), duty judgment of DCTL signal)
Clock source................ 1/2, (1/4,) 1/8, (1/16,) 1/12, (1/24) of system clock frequency
Interrupt source ........... overflow of timer counter 2; input of DCTL specified edge; underflow of timer 2 shift register 4-bit
counter; coincidence of timer 2 shift register with timer 2 shift register compare register
Timer counter 3 : 16-bit × 1
(timer function, detection of serial indexing, generation of remote control output carrier frequency)
Clock source................ 1/2, (1/4,) 1/8, (1/16) of system clock frequency; XI oscillation clock
Interrupt source ........... overflow of timer counter 3
Timer counter 4 : 16-bit × 1 (timer function, event count [P15 input], generation of serial transmission clock)
Clock source................ 1/8, (1/16) of system clock frequency; external clock input
Interrupt source ........... overflow of timer counter 4; coincidence of timer counter 4 with OCR4
Timer counter 5 : 19-bit × 1 (watchdog, stable oscillation waiting function)
Clock source................ system clock
Watchdog interrupt source... 1/2¹⁶, 1/2¹⁹ of timer counter 5 frequency
Clear by stable oscillation ... after 256 counts by timer counter 5 (218 counts of OSC oscillation clock)
Timer counter 6 : 16-bit × 1 (clock function [max. 2 s])
Clock source................ 1/512 of OSC oscillation clock frequency; XI oscillation clock; 1/4, (1/8,) 1/64, (1/128) of system clock
frequency
Interrupt source ........... 1/2¹³, 1/2¹⁴, 1/2¹⁵ overflow of timer counter 6
Timer counter 7 : 8-bit × 1 or 4-bit × 2 (timer function, event count)
Clock source................ 1/4, (1/8,) 1/16, (1/32) of system clock frequency; external clock input
Interrupt source ........... overflow of timer counter 7 (although when 4-bit × 2, there is one interrupt vector. )
MAD00030GEM