OX16PCI954 Datasheet, PDF (3/72 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX16PCI954
7.5.2 LINE CONTROL REGISTER ‘LCR’ ........................................................................................................................ 36
7.5.3 LINE STATUS REGISTER ‘LSR’............................................................................................................................ 37
7.6 INTERRUPTS & SLEEP MODE................................................................................................................................. 38
7.6.1 INTERRUPT ENABLE REGISTER ‘IER’................................................................................................................. 38
7.6.2 INTERRUPT STATUS REGISTER ‘ISR’................................................................................................................. 39
7.6.3 INTERRUPT DESCRIPTION.................................................................................................................................. 39
7.6.4 SLEEP MODE ....................................................................................................................................................... 40
7.7 MODEM INTERFACE................................................................................................................................................ 40
7.7.1 MODEM CONTROL REGISTER ‘MCR’.................................................................................................................. 40
7.7.2 MODEM STATUS REGISTER ‘MSR’ ..................................................................................................................... 41
7.8 OTHER STANDARD REGISTERS............................................................................................................................. 41
7.8.1 DIVISOR LATCH REGISTERS ‘DLL & DLM’ .......................................................................................................... 41
7.8.2 SCRATCH PAD REGISTER ‘SPR’......................................................................................................................... 41
7.9 AUTOMATIC FLOW CONTROL ................................................................................................................................ 42
7.9.1 ENHANCED FEATURES REGISTER ‘EFR’ ........................................................................................................... 42
7.9.2 SPECIAL CHARACTER DETECTION .................................................................................................................... 43
7.9.3 AUTOMATIC IN-BAND FLOW CONTROL.............................................................................................................. 43
7.9.4 AUTOMATIC OUT-OF-BAND FLOW CONTROL .................................................................................................... 43
7.10 BAUD RATE GENERATION...................................................................................................................................... 44
7.10.1 GENERAL OPERATION........................................................................................................................................ 44
7.10.2 CLOCK PRESCALER REGISTER ‘CPR’................................................................................................................ 44
7.10.3 TIMES CLOCK REGISTER ‘TCR’ .......................................................................................................................... 44
7.10.4 EXTERNAL 1X CLOCK MODE .............................................................................................................................. 46
7.10.5 CRYSTAL OSCILLATOR CIRCUIT ........................................................................................................................ 46
7.11 ADDITIONAL FEATURES ......................................................................................................................................... 46
7.11.1 ADDITIONAL STATUS REGISTER ‘ASR’............................................................................................................... 46
7.11.2 FIFO FILL LEVELS ‘TFL & RFL’............................................................................................................................. 47
7.11.3 ADDITIONAL CONTROL REGISTER ‘ACR’ ........................................................................................................... 47
7.11.4 TRANSMITTER TRIGGER LEVEL ‘TTL’ ................................................................................................................ 48
7.11.5 RECEIVER INTERRUPT. TRIGGER LEVEL ‘RTL’ ................................................................................................. 48
7.11.6 FLOW CONTROL LEVELS ‘FCL’ & ‘FCH’ .............................................................................................................. 48
7.11.7 DEVICE IDENTIFICATION REGISTERS................................................................................................................ 48
7.11.8 CLOCK SELECT REGISTER ‘CKS’ ....................................................................................................................... 49
7.11.9 NINE-BIT MODE REGISTER ‘NMR’....................................................................................................................... 49
7.11.10 MODEM DISABLE MASK ‘MDM’............................................................................................................................ 50
7.11.11 READABLE FCR ‘RFC’.......................................................................................................................................... 50
7.11.12 GOOD-DATA STATUS REGISTER ‘GDS’.............................................................................................................. 50
8 LOCAL BUS...............................................................................................................................................51
8.1 OVERVIEW ............................................................................................................................................................... 51
8.2 OPERATION ............................................................................................................................................................. 51
8.3 CONFIGURATION & PROGRAMMING...................................................................................................................... 52
9 BIDIRECTIONAL PARALLEL PORT .......................................................................................................53
9.1 OPERATION AND MODE SELECTION ..................................................................................................................... 53
9.1.1 SPP MODE ........................................................................................................................................................... 53
9.1.2 PS2 MODE............................................................................................................................................................ 53
9.1.3 EPP MODE ........................................................................................................................................................... 53
9.1.4 ECP MODE (NOT SUPPORTED) .......................................................................................................................... 53
9.2 PARALLEL PORT INTERRUPT ................................................................................................................................ 53
9.3 REGISTER DESCRIPTION........................................................................................................................................ 54
9.3.1 PARALLEL PORT DATA REGISTER ‘PDR’ ........................................................................................................... 54
9.3.2 DEVICE STATUS REGISTER ‘DSR’ ...................................................................................................................... 54
9.3.3 DEVICE CONTROL REGISTER ‘DCR’................................................................................................................... 55
9.3.4 EPP ADDRESS REGISTER ‘EPPA’ ....................................................................................................................... 55
9.3.5 EPP DATA REGISTERS ‘EPPD1-4’ ....................................................................................................................... 55
9.3.6 EXTENDED CONTROL REGISTER ‘ECR’ ............................................................................................................. 55
Data Sheet Revision 1.3
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