OXU121HP Datasheet, PDF(16/22 Page) Oxford Semiconductor – USB On-The-Go Full-Speed Host and High-Speed Peripheral Controller

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OXU121HP Datasheet, PDF (16/22 Pages) Oxford Semiconductor – USB On-The-Go Full-Speed Host and High-Speed Peripheral Controller

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OXU121HP Data Sheet

Oxford Semiconductor, Inc.

Table 14 OXU121HP 84-Ball BGA Pin Allocations (Sheet 2 of 3)

No. Type(1)

Bits

1 5I

Name

VBUS

Description

VBUS input used by the voltage comparators of the OTG

port for connection. This pin should be left floating in a

host only application

1 OC

VBP

VBUS pulsing control. This pin is used only when the

OTG port is operating as a B-device

1 P5O

/EXVBO

Turn on/off the external VBUS (5 V) for OTG operation

(1:VBUS off, 0:VBUS on) when using the external charge

pump

H10

1 IU

/OC

Over current condition indicator for powered host ports.

Pull-up is always enabled

RREF

Connect external reference resistor (12 Kâ¦ +/- 1%) to

VSSA

1 IU

Connected to the ID pin of the mini-AB connector for

OTG applications. With the help of an internal pull-up

resistor, this pin determines the chipâs responsibility in an

OTG application (0: A-device, 1:B-device). Pull-up can be

disabled through register 0x038, bits 7:6. Default is pull-

G10

1 P5O

Clock Interface (3 pins)

K10

/PO

OSC1

OSC2

CLKCFG

Internal VBUS Charge Pump (3 pins)

D10

E10

Internal Voltage Regulator (2 pins)

PD_PMOS

EXT

VOUT

ENVREG

VREGOUT

Turn on/off gang power for all host ports

Input. A 12 MHz or 30 MHz passive crystal should be

connected across the two pins (OSC1 and OSC2).

Optionally, a 12 MHz or 30 MHz oscillator can be

connected to OSC1 while keeping OSC2 unconnected

Output

Indicates whether a 12 MHz or a 30 MHz crystal/oscillator

is being used.

0 = 12 MHz crystal or 12 MHz 3.3 V oscillator input on

OSC1

1 = 30 MHz crystal or 30 MHz 3.3 V oscillator input on

OSC1

Internal charge pump output for P-MOSFET (optional

switch on the VOUT)

Internal charge pump output for N-MOSFET

Internal charge pump output voltage feedback pin

Enables the internal voltage regulator if asserted. If not

used, this pin should be tied to VSS

Internal voltage regulator output of 1.8 V. If enabled, this

output should be connected to the VDD1.8, (and VDDW if

wide-range IO is at 1.8 V) supplies of the chip. If the

regulator is disabled, then this pin should be treated as

another VDD1.8 supply input to the chip

External--Free Release

DS-0040 Aug 06

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