TRSL-9115WG Datasheet, PDF (4/5 Pages) Optoway Technology Inc – 3.3V / 1310 nm / 2.5 Gbps RoHS Compliant SFF LC 2X10 SINGLE-MODE TRANSCEIVER

Optoway
4
TRSL-9115WG
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CONNECTION DIAGRAM
PIN Symbol
Notes
PIN Symbol
Notes
1 VpdR Receiver power monitor. This pin must be 11 VccT +3.3V dc transmitter power supply
connected to a positive power supply (Vcc),
preferably via a small resistor. Supplier
photocurrent and maybe used to monitor receiver
power.
2 VeeR Receiver ground.
12 VeeT Transmitter ground.
3 VeeR Receiver ground.
13 T Dis Transmitter Disable. Connect this pin to logic “1”
to disable module. To enable module connect to
logic low “0”
4 NC No connected
14 TD + Transmitter Data In
5 NC No connected
15 TD − Transmitter Data In Bar
6 VeeR Receiver ground.
16 VeeT Transmitter ground.
7 VccR +3.3V dc receiver power supply
17 Bmon− Laser Bias Monitoring – Negative End
8 SD Signal detect. Logic 1 indicate a normal operation. 18 Bmon+ Laser Bias Monitoring – Positive End
(Bmon+ - Bmon-) = 10 Ω X laser bias current
9 RD− Receiver Dataout Bar
19 Pmon- Laser Power Monitoring -- Negative end
10 RD+ Receiver Dataout
20 Pmon+ Laser Power Monitoring -- Positive end
(Pmon+ - Pmon-) = 200 Ω X monitor photdiode
current
MS MS Mounting Studs. Connect to Chassis Ground
RECOMMENDED CIRCUIT SCHEMATIC
Tdis(LVTTL)
Bmon-
Bmon+
Pmon-
Pmon+
TX
MICROSTRIP5
Z=50R
MICROSTRIP6
Z=5OR
L2
1uH
C2
100nF
L1
1uH
VCC3.3V
C3
100nF
C4
10uF
Vcc3.3V
TD-
LVPECL
TD+
PHY DEVICE
RX
C1
C8
100nF 10uF
Vcc3.3V
RD+
VCCRX(3.3V)
Vpdr
200R
10nF
3K
MICROSTRIP7
Z=50R
MICROSTRIP8
Z=5OR
R14
100R
RD-
LVPECL
SD
TO LVTTL STAGE
Note: 1. TX input is terminated inside the module.
2. Veer and Veet are not internally connected to each other.
3. 50 Ω line pattern and component placements on TD+/TD- and RD+/RD- lines shall be symmetrical for better impedance
matching.
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OPTOWAY TECHNOLOGY INC. No.38, Kuang Fu S. Road, Hu Kou, Hsin Chu Industrial Park, Hsin Chu, Taiwan 303
Tel: [phone]
Fax: [phone]
E-mail: [e-mail] http: // www.optoway.com.tw 12/1/2005 V3.0