CAT9534 Datasheet, PDF (9/16 Pages) ON Semiconductor – 8-bit I²C and SMBus I/O Port with Interrupt

CAT9534
ACKNOWLEDGE
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8
bits of data. The SDA line remains stable LOW during
the HIGH period of the acknowledge related clock
pulse (Figure 5).
The CAT9534 responds with an acknowledge after
receiving a START condition and its slave address. If
the device has been selected along with a write
operation, it responds with an acknowledge after
receiving each 8-bit byte.
When the CAT9534 begins a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT9534 will continue to transmit
data. If no acknowledge is sent by the Master, the
device terminates data transmission and waits for a
STOP condition. The master must then issue a STOP
condition to return the CAT9534 to the standby power
mode and place the device in a known state.
REGISTERS AND BUS TRANSACTIONS
The CAT9534 consists of an input port register, an
output port register, a polarity inversion register and a
configuration register. Table 1 shows the register
address table. Tables 2 to 5 list Register 0 through
Register 3 information.
Table 1. Register Command Byte
Command
(hex)
0x00
0x01
0x02
0x03
Protocol
Read byte
Read/write byte
Read/write byte
Read/write byte
Function
Input port register
Output port register
Polarity inversion register
Configuration register
The command byte is the first byte to follow the device
address byte during a write/read bus transaction. The
register command byte acts as a pointer to determine
which register will be written or read.
The input port register is a read only port. It reflects
the incoming logic levels of the I/O pins, regardless of
whether the pin is defined as an input or an output by
the configuration register. Writes to the input port
register are ignored.
Table 2. Register 0 – Input Port Register
bit
I₇ I₆ I₅ I₄ I₃ I₂ I₁ I₀
default 1 1 1 1 1 1 1 1
Table 3. Register 1 – Output Port Register
bit
O₇ O₆ O₅ O₄ O₃ O₂ O₁ O₀
default 1 1 1 1 1 1 1 1
Table 4. Register 2 – Polarity Inversion Register
bit
N₇ N₆ N₅ N₄ N₃ N₂ N₁ N₀
default 0 0 0 0 0 0 0 0
Table 5. Register 3 – Configuration Register
bit
C₇ C₆ C₅ C₄ C₃ C₂ C₁ C₀
default 1 1 1 1 1 1 1 1
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER)
1
8
BUS RELEASE DELAY (RECEIVER)
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY
ACK SETUP
Figure 7. Acknowledge Timing
© 2010 SCILLC. All rights reserved
9
Characteristics subject to change without notice
Doc. No. MD-9004 Rev. D