CAT3636 Datasheet, PDF (9/14 Pages) Catalyst Semiconductor – 6-Channel Quad-ModeTM Fractional LED Driver in TQFN3x3

CAT3636
LED Current Setting
The current in each of the six LED channels is
programmed through the 1−wire EN/SET digital control
input. By pulsing this signal according to a specific protocol,
a set of internal registers can be addressed and written into
allowing to configure each bank of LEDs with the desired
current. There are six registers: the first five are 4 bits long
and the sixth is 1 bit long. The registers are programmed by
first selecting the register address and then programming
data into that register.
An internal counter records the number of falling edges to
identify the address and data. The address is serially
programmed adhering to low and high duration time delays.
One down pulse corresponds to register 1 being selected.
Two down pulses correspond to register 2 being selected and
so on up to register 6. T_LO and T_HI must be within 200 ns to
100 ms. Anything below 200 ns may be ignored.
Once the final rising edge of the address pointer is
programmed, the user must wait 500 ms to 1000 ms before
programming the first data pulse falling edge. If the falling
edge of the data is not received within 1000 ms, the device
will revert back to waiting for an address.
Data in a register is reset once it is selected by the address
pointer. If a register is selected but no data is programmed,
then the register value is reset back to its initial default value
with all data bits to 0.
Once the final rising edge of the data pulses is
programmed, the user must wait 1.5 ms before
programming another address. If programming fails or is
interrupted, the user must wait T_RESETDELAY 2 ms from the
last rising edge before reprogramming can commence.
Upon power−up, the device automatically starts looking
for an address. The device requires a minimum 10 ms delay
(T_SETUP) to ensure the initialization of the internal logic at
power−up. After this time delay, the device registers may be
programmed adhering to the timing constraints shown in
Figure 21. If no falling edge is detected within 100 ms of
power−up, then the user must wait 2 ms before trying to
program the device again.
To power−down the device and turn−off all current
sources, the EN/SET input should be kept low for a duration
T_OFF of 1.5 ms or more. The driver typically powers−down
with a delay of about 1 ms. All register data are lost.
Figure 21. EN/SET One Wire Addressable Timing Diagram
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