CAT34TS02_14 Datasheet, PDF (9/21 Pages) ON Semiconductor – Digital Output Temperature Sensor

CAT34TS02
Write Operations
EEPROM Byte and TS Register Write
To write data to a TS register, or to the on−board
EEPROM, the Master creates a START condition on the bus,
and then sends out the appropriate Slave address (with the
R/W bit set to ‘0’), followed by an address byte and data
byte(s). The matching Slave will acknowledge the Slave
address, EEPROM byte address or TS register address and
the data byte(s), one for EEPROM data (Figure 24) and two
for TS register data (Figure 25). The Master then ends the
session by creating a STOP condition on the bus. The STOP
completes the (volatile) TS register update or starts the
internal Write cycle for the (non−volatile) EEPROM data
(Figure 26).
EEPROM Page Write
The on−board EEPROM contains 256 bytes of data,
arranged in 16 pages of 16 bytes each. A page is selected by
the 4 most significant bits of the address byte immediately
following the Slave address, while the 4 least significant bits
point to the byte within the page. Up to 16 bytes can be
written in one Write cycle (Figure 27).
The internal EEPROM byte address counter is
automatically incremented after each data byte is loaded. If
the Master transmits more than 16 data bytes, then earlier
data will be overwritten by later data in a ‘wrap−around’
fashion within the selected page. The internal Write cycle,
using the most recently loaded data, then starts immediately
following the STOP.
Acknowledge Polling
Acknowledge polling can be used to determine if the
CAT34TS02 is busy writing to EEPROM, or is ready to
accept commands. Polling is executed by interrogating the
device with a ‘Selective Read’ command (see READ
OPERATIONS). The CAT34TS02 will not acknowledge
the Slave address as long as internal EEPROM Write is in
progress.
Delivery State
The CAT34TS02 is shipped ‘unprotected’, i.e. neither
Software Write Protection (SWP) flag is set. The entire
2−Kb memory is erased, i.e. all bytes are 0xFF.
BUS ACTIVITY: S
T
A
MASTER ^R
T
SPD
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
DATA
O
P
SDA LINE S
P
SLAVE
A
A
A
C
C
C
K
K
K
Figure 24. EEPROM Byte Write
BUS ACTIVITY: S
T
A
MASTER ^R
T
SDA LINE S
SLAVE
TS
SLAVE
ADDRESS
REGISTER
ADDRESS
DATA (MSB)
S
T
DATA (LSB)
O
P
P
A
A
A
A
C
C
C
C
K
K
K
K
Figure 25. Temperature Sensor Register Write
SCL
SDA
8th Bit
Byte n
ACK
t_WR
STOP
CONDITION
Figure 26. EEPROM Write Cycle Timing
START
CONDITION
ADDRESS
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