English
Language : 

CAT34TS02_14 Datasheet, PDF (14/21 Pages) ON Semiconductor – Digital Output Temperature Sensor
CAT34TS02
Table 10. CAPABILITY REGISTER
B15
B14
B13
RFU
RFU
RFU
B7
B6
B5
EVSD
TMOUT
RFU
B12
B11
RFU
RFU
B4
B3
TRES [1:0]
B10
RFU
B2
RANGE
B9
RFU
B1
ACC
B8
RFU
B0
EVENT
Bit
Description
B15:B8
Reserved for future use; can not be written; should be ignored; will read as 0
B7 (Note 13)
0:
1:
Configuration Register bit 4 is frozen upon Configuration Register bit 8 being set
(i.e. a TS shut−down freezes the EVENT output)
Configuration Register bit 4 is cleared upon Configuration Register bit 8 being set
(i.e. a TS shut−down de−asserts the EVENT output)
B6
0:
The TS implements SMBus time−out within the range 10 to 60 ms
1:
The TS implements SMBus time−out within the range 25 to 35 ms
B5
B4:B3
0:
Pin A0 VHV compliance required for RSWP Write/Clear operations not explicitly stated
1:
Pin A0 VHV compliance required for RSWP Write/Clear operations explicitly stated
00:
LSB = 0.50°C (9 bit resolution)
01:
LSB = 0.25°C (10 bit)
10:
LSB = 0.125°C (11 bit)
11:
LSB = 0.0625°C (12 bit)
B2
0:
Positive Temperature Only
1:
Positive and Negative Temperature
B1
0:
±2°C over the active range and ±3°C over the operating range (Class C)
1:
±1°C over the active range and ±2°C over the monitor range (Class B)
B0
0:
Critical Temperature only
1:
Alarm and Critical Temperature
13. Configuration Register bit 4 can be cleared (but not set) after Configuration Register bit 8 is set, by writing a “1” to Configuration Register
bit 5 (EVENT output can be de-asserted during TS shut-down periods)
http://onsemi.com
14