CAT3211 Datasheet, PDF (9/14 Pages) ON Semiconductor – Programmable Haptic Driver for Rotary DC Motors

CAT3211
eliminating any shoot−through current spikes. Internal
clamping diodes on the NEG pin safely dissipate any
inductive load current spikes back into PGND or REG nodes.
REG is the LDO regulated output which is connected to the
input of the H−bridge. A small 1 mF ceramic bypass capacitor
is required in close proximity across the REG pin and the
PGND pin. The LDO output voltage setting is stored in the
LDOH or LDOV registers depending on the mode selected,
haptic or vibrate respectively. The LDO regulator prevents
the motor from being overdriven by reducing the amplitude
of the voltage applied to the H−bridge and thus the motor.
OSC is the external oscillator logic input pin. The haptic
timer clock can be selected from the internal oscillator (1 ms
time base with ±20% accuracy) or from an external
oscillator if a higher precision is required. The optional
external oscillator is connected to the OSC pin. Selection of
the external oscillator is done by setting the OSC register
EXT_OSC bit (B0) high (1). The external and internal
oscillator frequency can be divided from 0 to 128 times via
bits B1, B2 & B3 in the OSC register. When the internal
oscillator is used, the OSC pin can be left unconnected.
When EXT_OSC bit is high, an internal watchdog monitors
the OSC pin signal. In haptic mode, if the OSC pin
rising−edge to rising−edge duration is longer than the
watchdog timeout (8 ms typical) then the haptic sequence is
aborted to prevent any motor damage.
SDA is the I²C serial data line, open−drain requiring an
external pull−up resistor as defined in the I²C standard. This
is a bidirectional data line allowing data to be written and
read from the registers. The voltage levels required for logic
high and logic low are 1.4 V and 0.4 V respectively. This
allows the interface to be directly connected to low voltage
processors.
SCL is the I²C serial clock input. The voltage levels required
for logic high and logic low are 1.4 V and 0.4 V respectively.
This allows the interface to be directly connected to low
voltage processors.
RST is the reset active low input logic pin. When the pin is
driven low, it resets all the internal registers to their default
values and shuts down the device. Once the RST input
returns to a logic high, the device is enabled again. The
voltage levels required for logic high and logic low are 1.4 V
and 0.4 V respectively.
Since the device has no power−on reset logic, it is
recommended that after power−up, the RST is set low for a
short time in order to reset all the registers.
GND is the ground reference for the input logic pins. The pin
must be connected to the ground plane on the PCB.
PGND is the ground reference for the H−bridge switches.
This pin carries the return current flowing through the
H−bridge via the POS and NEG pins and must be connected
to the ground plane.
Table 7. MODE SELECTION TRUTH TABLE
RST
(Pin)
CHIP_EN
(Reg)
VIB_EN
(Reg or
Pin)
H_TRIG
(Reg or
Pin)
H_REPT
(Reg)
0
X
X
X
X
1
0
X
X
X
1
1
0
0
0
1
1
0
1°
0
1
1
1
0
0
1
1
1
1°
0
1
1
X
X
1
REG PIN
SETTING
OFF : WEAK
PULLUP VIN
OFF : WEAK
PULLUP VIN
OFF : WEAK
PULLUP VIN
LDOH
Register Setting
LDOV
Register Setting
LDOH
Register Setting
LDOH
Register Setting
Operation Mode
Device Shutdown (VIB_EN & H_TRIG no operation).
No I²C interface programming possible.
Device Standby (VIB_EN & H_TRIG no operation).
I²C Interface programming possible
Device Standby (Awaiting signal from VIB_EN or H_TRIG).
Haptic mode sequence triggered on rising H_TRIG edge.
Vibrate mode enabled on VIB_EN logic high.
Haptic mode triggered.
Once Haptic sequence completes, device returns to vibrate
mode (REG = LDOV) until next haptic rising edge.
Haptic mode repeat enabled.
Haptic sequence will continuously repeat programmed
sequence. Ensure recovery time is correctly programmed
to prevent motor damage.
NOTE: X = DON’T CARE (Can be Logic High or Logic Low)
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