CAT3211 Datasheet, PDF (8/14 Pages) ON Semiconductor – Programmable Haptic Driver for Rotary DC Motors

CAT3211
Table 6. PIN DESCRIPTION
Pin No
Name
Function
1
RST
Device reset active low input.
2
SDA
I²C bidirectional data input/output, open−drain.
3
SCL
I²C clock input.
4
VIN
Supply input.
5
NEG
Connect to negative side of motor
6
PGND
Ground reference for the H−Bridge.
7
POS
Connect to positive side of motor.
8
REG
Connected to the internal LDO output.
9
OSC
External oscillator input (optional).
10
H_TRIG
External Haptic mode trigger input.
11
VIB_EN
External Vibrate mode enable input.
12
GND
Ground Reference for the device logic.
PIN FUNCTION
VIN is the supply voltage input pin for the device. A small
1 mF ceramic bypass capacitor is required in close proximity
across the VIN pin and the GND pin. The normal operating
supply voltage range is from 2.7 V to 5.5 V. An internal
under−voltage lock−out (UVLO) circuit will disable the
output drive current whenever the supply voltage falls below
approximately 2.0 V. The driver should not be operated for
a supply VIN below 2 V. If the supply dropped below 2.0 V
and VIN is restored, the device should be re−programmed to
the desired register setting.
VIB_EN is the vibrate enable logic input pin used to enable
the vibrate mode. The applied voltage levels required for
logic high and logic low are 1.4 V and 0.4 V respectively.
This allows direct connection to low voltage processors. An
internal pull−down resistor of 110 kW exists between the
VIB_EN pin and GND. When both VIB_EN and H_TRIG
are low, the device enters a standby mode. When the
VIB_EN pin is taken high, the H−Bridge turns on the output
in forward mode where the POS pin is connected to REG
(and the NEG pin to PGND). In order to protect from
overdriving the motor, the internal LDO regulates the
H−Bridge between VIN and 2 V according to the LDOV
register. If the RST or CHIP_EN bit in the CONFIG register
are low then VIB_EN input is ignored.
H_TRIG is the haptic logic input pin to trigger the haptic
pulse sequence. The applied voltage levels required for logic
high and logic low are 1.4 V and 0.4 V respectively. This
allows direct connection to low voltage processors. An
internal pull−down resistor of 110 kW exists between the
H_TRIG pin and GND. When both VIB_EN and H_TRIG
are low, the device enters a standby mode. On H_TRIG
rising edge, the H−bridge is activated with the following
haptic mode sequence: forward (POS connected to REG,
NEG connected to PGND), coast (both POS and NEG
disconnected), and reverse (POS connected to PGND, NEG
connected to REG). The haptic pulse timing is stored in the
two registers HAPTIC_A and HAPTIC_B. A recovery
timer prevents retriggering the haptic sequence until the
recovery time is over. The recovery timer can be configured
between 0 and 60 clock cycles according to the HAPTIC_B
register. The H_Bridge input voltage can be adjusted to ‘fine
tune’ the overdrive voltage by setting the internal LDO
regulator voltage using the LDOH register. If H_TRIG is
triggered while VIB_EN is high, then H_TRIG overrides
and sets off a haptic timer sequence. Once the haptic
sequence is finished, the device returns to normal VIB_EN
mode (forward direction and LDOV setting voltage). If the
RST or CHIP_EN bit in the CONFIG register are low, the
H_TRIG input is ignored.
POS is the positive output node of the internal H−bridge.
During normal operation, this pin has a drive resistance of
approx 0.4 W to either REG (LDO output) or to PGND,
depending on the direction being selected. The maximum
sourcing or sinking current at this pin is current limited to
850 mA typical. When the coast timer starts, the POS pin
immediately enters a high−impedance state. During any
forward/reverse transitions, the POS drive output exhibits a
break−before−make interval of approximately 2 ms,
eliminating any shoot−through current spikes. Internal
clamping diodes on the POS pin safely dissipate any
inductive load current spikes back into PGND or REG nodes.
NEG is the negative output node of the internal H−bridge.
During normal operation, this pin has a drive resistance of
0.4 W to either PGND or to REG (LDO output), depending
on the direction being selected. The maximum sinking or
sourcing current at this pin is current limited to 850 mA
typical. When the coast timer starts, the NEG pin
immediately enters a high−impedance state. During any
forward/reverse transitions, the NEG drive output exhibits
a break−before−make interval of approximately 2 ms,
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