NCP1351 Datasheet, PDF (8/19 Pages) ON Semiconductor – Variable Off Time PWM Controller

NCP1351
APPLICATION INFORMATION
The Negative Sensing Technique
Standard current−mode controllers use the positive
sensing technique as portrayed by Figure 4. In this
technique, the controller detects a positive voltage drop
across the sense resistor, representative of the flowing
current. Unfortunately, this solution suffers from the
following drawbacks:
1. Difficulties to precisely adjust the peak current. If
1 V is the maximum sense level, you must
combine low valued resistors to reach the exact
limit you need.
2. The voltage developed across the sense resistor
subtracts from the gate voltage. If your VCC_(min)
is 7 V, then the actual gate voltage at the end of the
on time, assuming a full load condition, is 7 V –
1 V = 6 V.
3. The current in the sense resistor also includes the
C_iss current at turn−on. This narrow spike often
disturbs the controller and requires adequate
treatment through a LEB circuitry for instance.
Figure 5 represents the negative current sense technique.
In this simplified example, the source directly connects to
the controller ground. Hence, if V_CC is 8 V, the effective
gate−source voltage is very close to 8 V: no sense resistor
drop. How does the controller detect a negative excursion?
In lack of primary current, the voltage on the CS pin reaches
R_offset x I_CS. Let us assume that these elements lead to have
1 V on this pin. Now, when the power MOSFET activates,
the current flows via the sense resistor and develop a
negative voltage by respect to the controller ground. The
voltage seen on the CS is nothing else than a positive voltage
(R_offset x I_CS) plus the voltage across the sense resistor which
is negative. Thus, the CS pin voltage goes low as the primary
current increases. When the result reaches the threshold
voltage (around 20 mV), the comparator toggles and resets
the main latch. Figure 3 details how the voltage moves on the
CS pin on a 1351 demoboard, whereas Figure 7 zooms on
the sense resistor voltage captured by respect to the
controller ground.
The choice of these two elements is simple. Suppose you
want to develop 1 V across the sense resistor. You would
select the offset resistor via the following formula:
Roffset
+
1
ICS
+
1
270
m
+
3.7
kW
(eq. 1)
If you need a peak current of 2 A, then, simply apply the
ohm law to obtain the sense resistor value:
Rsense
+
1
Ipeak_max
+
1
2
+
0.5
W
(eq. 2)
Due to the circuit flexibility, suppose you only have access
to a 0.33 W resistor. In that case, the peak current will exceed
the 2 A limit. Why not changing the offset resistor value
then? To obtain 2 A from the 0.33 W resistor, you should
develop:
The offset resistor is thus derived by:
Vsense + RsenseIpeak_max + 0.33 2 + 660 mV
(eq. 3)
Roffset
+
0.66
ICS
+
0.66
270 m
+
2.44
kW
(eq. 4)
If reducing the sense resistor is of good practice to
improve the efficiency, we recommend to adopt sense values
between 0.5 V and 1 V. Reducing the voltage below these
levels will degrade the noise immunity.
I_Lp
L_P
L_P
+
C_Bulk
I_Lp ^Reset
+
−
I_Lp
DRV
V_gs
CS
I_Lp
Peak
Setpoint ^Rsense
GND
V_sense
Figure 4. Positive Current−Sense Technique
DRV
V_DD
+
C_Bulk
ICS
CS
−
Reset ^GND
I_Lp
I_Lp
+
V_offset
R_{offset +}
V_th
I_Lp
V_sense
Figure 5. A Simplified Circuit of the Negative Sense
Implementation
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