NCP1351 Datasheet, PDF (16/19 Pages) ON Semiconductor – Variable Off Time PWM Controller

NCP1351
In this equation, the CCM duty−cycle does not exceed
50%. The design should thus be free of subharmonic
oscillations in steady−state conditions. If necessary,
negative ramp compensation is however feasible by the
auxiliary winding.
3. To obtain the primary inductance, we can use the
following equation which expresses the inductance
in relationship to a coefficient k. This coefficient
actually dictates the depth of the CCM operation.
If it goes to 2, then we are in DCM.
L + ^{(Vin_mind max)2}
FSWKPin
(eq. 21)
where K = DI_L/I_I and defines the amount of ripple we want
in CCM (see Figure 20).
• Small K: deep CCM, implying a large primary
inductance, a low bandwidth and a large leakage
inductance.
• Large K: approaching BCM where the RMS losses are
the worse, but smaller inductance, leading to a better
leakage inductance.
From Equation 16, a K factor of 0.8 (40% ripple) ensures a
good operation over universal mains. It leads to an
inductance of:
(100 43)2
L+
+ 493 mH
65 k 0.8 72
(eq. 22)
DIL
+
Vin_mind _max
LFSW
+
19
0.8
3
100
+ 1.34 A peak−to−peak
(eq. 23)
The peak current can be evaluated to be:
Iin_avg
+
Pout
h^Vin_min
+
100
493 m
0.43 _{+ 712 mA (eq. 24)}
65 k
Ipeak
+
Iavg
d
)
DIL
2
+
0.712
0.43
)
1.34
2
+
2.33
A
(eq. 25)
On Figure 20, I₁ can also be calculated:
II
+
Ipeak
*
DIL
2
+
2.33
*
1.34
2
+
1.65
A
(eq. 26)
The valley current is also found to be:
Ivalley + Ipeak * DIL + 2.33 * u1.34 + 1.0 A (eq. 27)
4. Based on the above numbers, we can now evaluate
the RMS current circulating in the MOSFET and
the sense resistor:
Ǹ _{ǒ Ǔ Id_rms + II} ^Ǹ_{d 1 )} ^{1 DIL} ₂
3 2I1
Ǹ _{ǒ Ǔ + 1.65 0.65}
1 ) ^{1 1.34 2}
3 2 1.65
(eq. 28)
+ 1.1 A
5. The current peaks to 2.33 A. Selecting a 1 V drop
across the sense resistor, we can compute its value:
Rsense
+
1
Ipeak
+
1
2.5
+
0.4
W
(eq. 29)
To generate 1 V, the offset resistor will be 3.7 kW, as already
explained. Using Equation 28, the power dissipated in the
sense element reaches:
Psense + Rsense Id_rms2 + 0.4 1.12 + 484 mW
(eq. 30)
6. To switch at 65 kHz, the C_t capacitor connected to
pin 2 will be selected to 180 pF.
7. As the load changes, the operating frequency will
automatically adjust to satisfy either equation 5
(high power, CCM) or equation 6 in lighter load
conditions (DCM).
Figure 21 portrays a possible application schematic
implementing what we discussed in the above lines.
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