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MC74HC161A Datasheet, PDF (8/16 Pages) ON Semiconductor – Presettable Counters | |||
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3
P0
P1 4
P2 5
P3 6
ENABLE P 7
ENABLE T 10
RESET 1
LOAD 9
CLOCK 2
T0
R
Q0
C
C
LOAD
LOAD Q0
P0
T1
R
Q1
C
C
LOAD
LOAD Q1
P1
T2
R
Q2
C
C
LOAD
LOAD Q2
P2
14 Q0
13 Q1
12 Q2
R
LOAD
LOAD
C
C
T3
R
Q3
C
C
LOAD
LOAD
P3
11 Q3
VCC = PIN 16
GND = PIN 8
15
RIPPLE
CARRY
OUT
The flipâflops shown in the circuit diagrams are ToggleâEnable flipâflops. A Toggleâ
Enable flipâflop is a combination of a D flipâflop and a T flipâflop. When loading data from
Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of
the flipâflop. The logic level at the Pn input is then clocked to the Q output of the flipâflop
on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal clock (C) high and resets the Q
output of the flipâflop low.
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