MC74HC161A Datasheet, PDF (10/16 Pages) ON Semiconductor – Presettable Counters

P0 ³
P1 ⁴
P2 ⁵
P3 ⁶
ENABLE P ⁷
ENABLE T ¹⁰
RESET ¹
LOAD ⁹
CLOCK ²
T0
R
Q0
C
C
LOAD
LOAD Q0
P0
T1
R
Q1
C
C
LOAD
LOAD Q1
P1
T2
R
Q2
C
C
LOAD
LOAD _Q2
P2
14 _Q0
13 _Q1
12
Q2
R
LOAD
LOAD
C
C
T3
R
Q3
C
C
LOAD
LOAD
P3
11 _Q3
VCC = PIN 16
GND = PIN 8
15
RIPPLE
CARRY
OUT
The flip–flops shown in the circuit diagrams are Toggle–Enable flip–flops. A Toggle–
Enable flip–flop is a combination of a D flip–flop and a T flip–flop. When loading data from
Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of
the flip–flop. The logic level at the Pn input is then clocked to the Q output of the flip–flop
on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal clock (C) high and resets the Q
output of the flip–flop low.