CAT93C66V-TE13 Datasheet, PDF (8/16 Pages) ON Semiconductor – 4 kb Microwire Serial CMOS EEPROM

CAT93C66, CAT93W66
Erase All
Upon receiving an ERAL command (Figure 7), the CS
(Chip Select) pin must be deselected for a minimum of
t_CSMIN. The falling edge of CS will start the self clocking
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
device can be determined by selecting the device and polling
the DO pin. Once cleared, the contents of all memory bits
return to a logical “1” state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
t_CSMIN (Figure 8). The falling edge of CS will start the self
clocking data write to all memory locations in the device.
The clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy status of
the device can be determined by selecting the device and
polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
SK
CS
STATUS VERIFY
STANDBY
t_CS
DI
1
00
10
HIGH−Z
DO
t_SV
BUSY _READY
t_EW
t_HZ
HIGH−Z
Figure 7. ERAL Instruction Timing
SK
CS
STATUS VERIFY STANDBY
t_CSMIN
DI
1
000
1
D_N
D₀
t_SV
t_HZ
DO
BUSY READY
HIGH−Z
t_EW
Figure 8. WRAL Instruction Timing
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