CAT5411WI-25 Datasheet, PDF (8/16 Pages) ON Semiconductor – Dual Digitally Programmable Potentiometers with 64 Taps and SPI Interface

CAT5411
INSTRUCTION AND REGISTER
DESCRIPTION
DEVICE TYPE / ADDRESS BYTE
The first byte sent to the CAT5411 from the master/
processor is called the Device Address Byte. The
most significant four bits of the Device Type address
are a device type identifier. These bits for the
CAT5411 are fixed at 0101[B] (refer to Table 1).
The two least significant bits in the slave address
byte, A1 - A0, are the internal slave address and must
match the physical device address which is defined by
the state of the A1 - A0 input pins for the CAT5411 to
successfully continue the command sequence. Only
the device which slave address matches the incoming
device address sent by the master executes the
instruction. The A1 - A0 inputs can be actively driven
by CMOS input signals or tied to V_CC or V_SS. The
remaining two bits in the device address byte must be
set to 0.
INSTRUCTION BYTE
The next byte sent to the CAT5411 contains the
instruction and register pointer information. The four
most significant bits used provide the instruction
opcode I [3:0]. The R1 and R0 bits point to one of the
four data registers of each associated potentiometer.
The least two significant bits point to one of two Wiper
Control Registers. The format is shown in Table 2.
Data Register Selection
Data Register Selected
DR0
DR1
DR2
DR3
R1
R0
0
0
0
1
1
0
1
1
Table 1. Identification Byte Format 0101 Device Type Identifier (MSB)
Device Type
Identifier
Slave Address
ID3
ID2
ID1
ID0
0
0
A1
A0
0
1
0
1
(MSB)
(LSB)
Table 2. Instruction Byte Format
Instruction
Opcode
I3
I2
I1
(MSB)
Data Register
Selection
I0
R1
R0
WCR/Pot
Selection
0
P0
(LSB)
Figure 3. Potentiometer Timing (for All Load Instructions)
CS
SCK
•••
SI
MSB
•••
V_W/R_W
High Impedance
SO
Doc. No. MD-2114 Rev. K
8
t_WRL
LSB
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Characteristics subject to change without notice