CAT5411WI-25 Datasheet, PDF (1/16 Pages) ON Semiconductor – Dual Digitally Programmable Potentiometers with 64 Taps and SPI Interface

CAT5411
Dual Digitally Programmable Potentiometers (DPP™)
with 64 Taps and SPI Interface
FEATURES
„ Two linear-taper digitally programmable
potentiometers
„ 64 resistor taps per potentiometer
„ End to end resistance 2.5kΩ, 10kΩ, 50kΩ or
100kΩ
„ Potentiometer control and memory access via
SPI interface: Mode (0, 0) and (1, 1)
„ Low wiper resistance, typically 80
„ Nonvolatile memory storage for up to four
wiper settings for each potentiometer
„ Automatic recall of saved wiper settings at
power up
„ 2.5 to 6.0 volt operation
„ Standby current less than 1µA
„ 24-lead SOIC and 24-lead TSSOP
„ Industrial temperature ranges
DESCRIPTION
The CAT5411 is two Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists
of a series of 63 resistive elements connected
between two externally accessible end points. The tap
points between each resistive element are connected
to the wiper outputs with CMOS switches. A separate
6-bit control register (WCR) independently controls
the wiper tap switches for each DPP. Associated with
each wiper control register are four 6-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a SPI serial
bus. On power-up, the contents of the first data
register (DR0) for each of the two potentiometers is
automatically loaded into its respective wiper control
register.
The CAT5411 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
SOIC (W)
(top view)
V_CC 1
24 NC
R_L0 2
23 NC
R_H0 3
22 NC
R_W0 4
21 NC
¯C¯S¯ 5
20 A₀
¯W¯P¯ 6 _CAT 19 SO
SI 7 ⁵⁴¹¹ 18 H¯¯O¯L¯D¯
A₁ 8
17 SCK
R_L1 9
16 NC
R_H1 10
15 NC
R_W1 11
14 NC
GND 12
13 NC
TSSOP (Y)
(top view)
SI 1
24 ¯W¯P¯
A₁ 2
23 ¯C¯S¯
R_L1 3
22 R_W0
R_H1 4
21 R_H0
R_W1 5
20 R_L0
GND 6 _CAT 19 V_CC
NC 7 ⁵⁴¹¹ 18 NC
NC 8
17 NC
NC 9
16 NC
NC 10
15 NC
SCK 11
14 A₀
H¯¯O¯L¯D¯ 12
13 SO
FUNCTIONAL DIAGRAM
R_H0 R_H1
CS
SCK
SI
SO
WP
A0
A1
SPI BUS
INTERFACE
WIPER
CONTROL
REGISTERS
R_W0
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
R_W1
R_L0 R_L1
For Ordering Information details, see page 15.
© 2008 SCILLC. All rights reserved.
1
Characteristics subject to change without notice
Doc. No. MD-2114 Rev. K