CAT5269WI-50 Datasheet, PDF (8/16 Pages) ON Semiconductor – Dual Digitally Programmable Potentiometers with 256 Taps and 2-wire Interface

CAT5269
INSTRUCTION AND REGISTER
DESCRIPTION
SLAVE ADDRESS BYTE
The first byte sent to the CAT5269 from the
master/processor is called the Slave/DPP Address
Byte. The most significant four bits of the slave
address are a device type identifier. These bits for the
CAT5269 are fixed at 0101[B] (refer to Table 1).
The next four bits, A3 - A0, are the internal slave
address and must match the physical device address
which is defined by the state of the A3 - A0 input pins
for the CAT5269 to successfully continue the
command sequence. Only the device which slave
address matches the incoming device address sent by
the master executes the instruction. The A3 - A0
inputs can be actively driven by CMOS input signals
or tied to V_CC or V_SS.
INSTRUCTION BYTE
The next byte sent to the CAT5269 contains the
instruction and register pointer information. The four
most significant bits used provide the instruction
opcode I3 - I0. The R1 and R0 bits point to one of the
four data registers of each associated potentiometer.
The least two significant bits point to one of four Wiper
Control Registers. The format is shown in Table 2.
Data Register Selection
Data Register Selected R1 R0
DR0
0
0
DR1
0
1
Figure 6. Write Timing
S
T ^{SLAVE/DPP INSTRUCTION}
S
BUS ACTIVITY: ^{A ADDRESS}
BYTE
T
MASTER ^R
T
Fixed
Variable
op code
Register Pot1 WCR _{DR1 WCRDATA}
Address Address
O
P
SDA LINE S
P
A
A
A
C
C
C
K
K
K
Table 1. Identification Byte Format
Device Type
Identifier
ID3
ID2
ID1
ID0
A3
0
1
0
1
(MSB)
Slave Address
A2
A1
A0
(LSB)
Table 2. Instruction Byte Format
Instruction
Opcode
I3
I2
I1
(MSB)
Data Register
Selection
WCR/Pot Selection
I0
R1
R0
P1
P0
(LSB)
Doc. No. MD-2123 Rev. E
8
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice