CAT5269WI-50 Datasheet, PDF (7/16 Pages) ON Semiconductor – Dual Digitally Programmable Potentiometers with 256 Taps and 2-wire Interface

Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
Figure 3. Start/Stop Condition
CAT5269
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
SDA
SCL
START CONDITION
Figure 4. Acknowledge Condition
SCL FROM
1
MASTER
STOP CONDITION
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
CAT5269 0 1 0 1 A3 A2 A1 A0
* A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.
** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
© 2008 SCILLC. All rights reserved.
7
Characteristics subject to change without notice
Doc. No. MD-2123 Rev. E