STK534U342C-E Datasheet, PDF (7/15 Pages) ON Semiconductor – Intelligent Power Module (IPM)

Input / Output Timing Chart
ON
HIN1,2,3
OFF
LIN1,2,3
STK534U342C-E
VBS undervoltage protection reset signal
VDD
VB1,2,3
ITRIP terminal
Voltage
VDD undervoltage protection reset voltage
*2
*3VBS ^{undervoltage protection reset voltage}
VIT≥0.54V
*4
VIT<0.44V
FLTEN
ON
*1
Upper
U, V, W
OFF
*1
Lower
U ,V, W
Automatically reset after protection
(typ.2ms)
Fig. 7
Notes
1. *1 shows the prevention of shoot-thru via control logic, however, more dead time must be added to account for switching
delay externally.
2. *2 when VDD decreases all gate output signals will go low and cut off all 6 IGBT outputs. When VDD rises the operation
will resume immediately.
3. *3 when the upper side voltage at VB1, VB2 and VB3 drops only the corresponding upper side output is turned off. The
outputs return to normal operation immediately after the upper side gate voltage rises.
4. *4 when VITRIP exceeds threshold all IGBT’s are turned off and normal operation resumes 2ms (typ) after over current
condition is removed.
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