MC74LVX259_05 Datasheet, PDF (7/10 Pages) ON Semiconductor – 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter with LSTTL−Compatible Inputs

MC74LVX259
ORDERING INFORMATION
Device
Package
Shipping^†
MC74LVX259D
SOIC−16
48 Units / Rail
MC74LVX259DG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74LVX259DR2
SOIC−16
2500 Tape & Reel
MC74LVX259DR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
MC74LVX259DT
TSSOP−16*
96 Units / Rail
MC74LVX259DTR2
TSSOP−16*
2500 Tape & Reel
MC74LVX259M
SOEIAJ−16
50 Units / Rail
MC74LVX259MG
SOEIAJ−16
(Pb−Free)
50 Units / Rail
MC74LVX259MEL
SOEIAJ−16
2000 Tape & Reel
MC74LVX259MELG
SOEIAJ−16
(Pb−Free)
2000 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
EMBOSSED CARRIER DIMENSIONS (See Notes 6 and 7)
Tape B₁
Size Max
D
D₁
E
F
K
P
P₀
P₂
R
T
W
8 mm 4.35 mm
(0.179”)
12 mm 8.2 mm
(0.323”)
1.5 mm
+ 0.1
−0.0
(0.059”
+0.004
−0.0)
1.0 mm
Min
(0.179”)
1.5 mm
Min
(0.060)
1.75 mm
±0.1
(0.069
±0.004”)
3.5 mm
±0.5
(1.38
±0.002”)
5.5 mm
±0.5
(0.217
±0.002”)
2.4 mm
Max
(0.094”)
6.4 mm
Max
(0.252”)
4.0 mm
±0.10
(0.157
±0.004”)
4.0 mm
±0.10
(0.157
±0.004”)
8.0 mm
±0.10
(0.315
±0.004”)
4.0 mm
±0.1
(0.157
±0.004”)
2.0 mm
±0.1
(0.079
±0.004”)
25 mm
(0.98”)
30 mm
(1.18”)
0.6 mm
(0.024)
8.3 mm
(0.327)
12.0 mm
±0.3
(0.470
±0.012”)
16 mm 12.1 mm
(0.476”)
7.5 mm
±0.10
(0.295
±0.004”)
7.9 mm
Max
(0.311”)
4.0 mm
±0.10
(0.157
±0.004”)
8.0 mm
±0.10
(0.315
±0.004”)
12.0 mm
±0.10
(0.472
±0.004”)
16.3 mm
(0.642)
24 mm 20.1 mm
(0.791”)
11.5 mm
±0.10
(0.453
±0.004”)
11.9 mm
Max
(0.468”)
16.0 mm
±0.10
(0.63
±0.004”)
24.3 mm
(0.957)
6. Metric Dimensions Govern−English are in parentheses for reference only.
7. A₀, B₀, and K₀ are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0.50 mm max. The component cannot rotate more than 10° within the determined cavity
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