MC74LVX259_05 Datasheet, PDF (6/10 Pages) ON Semiconductor – 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter with LSTTL−Compatible Inputs

MC74LVX259
TIMING REQUIREMENTS Input t_r = t_f = 3.0 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ T_A = 25°C
T_A = ≤ 85°C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol
Parameter
Test Conditions Min Typ Max Min Max Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ t_w
Minimum Pulse Width, Reset or Enable
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{(Figure 8)}
V_CC = 2.7 V
4.5
−
−
5.0
−
ns
V_CC = 3.3 V ± 0.3 V 4.5
−
−
5.0
−
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ t_su
Minimum Setup Time, Address or Data to Enable V_CC = 2.7 V
4.0
−
−
4.0
−
ns
(Figure 8)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ V_CC=3.3V±0.3V 3.0
−
−
3.0
−
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ t_h
Minimum Hold Time, Enable to Address or Data V_CC = 2.7 V
2.0
−
−
2.0
−
ns
(Figure 7 or 8)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ V_CC=3.3V±0.3V 2.0
−
−
2.0
−
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ t_r, t_f Maximum Input, Rise and Fall Times
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{(Figure 5)}
V_CC = 2.7 V
−
V_CC = 3.3 V ± 0.3 V
−
−
400
−
300
ns
−
300
−
300
V_CC
t_r
DATA
IN
t_PLH
50%
OUTPUT
Q
50%
DATA
t_f
IN
V_CC
ADDRESS
SELECT
50%
t_PHL
GND
50%
t_PHL
OUTPUT
Q
50%
t_PHL
GND
V_CC
GND
V_CC
GND
Figure 5. Switching Waveform
Figure 6. Switching Waveform
DATA IN
ENABLE
OUTPUT Q
t_w
50%
t_PHL
t_w
50%
50%
t_PHL
V_CC
GND
DATA IN
V_CC
RESET
GN
D
OUTPUT Q
t_w
50%
t_PHL
50%
V_CC
GND
V_CC
GND
Figure 7. Switching Waveform
Figure 8. Switching Waveform
DATA IN OR
ADDRESS
SELECT
50%
ENABLE
t_h(H)
t_su
t_su
50%
Figure 9. Switching Waveform
TEST POINT
V_CC
t_h(H)
GND
V_CC
OUTPUT
DEVICE
UNDER
TEST
C_L*
GND
*Includes all probe and jig capacitance
Figure 10. Test Circuit
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