MC100EPT24_16 Datasheet, PDF (7/8 Pages) ON Semiconductor – LVTTL/LVCMOS to Differential LVECL Translator

MC100EPT24
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
CASE 948R−02
ISSUE A
0.15 (0.006) T U S
2X L/2
L
PIN 1
IDENT
0.15 (0.006) T U S
8x K REF
0.10 (0.004) M T U S V S
8
5
B
−U−
1
4
A
−V−
0.25 (0.010)
M
F
DETAIL E
C
0.10 (0.004)
−T− SEATING
D
PLANE
G
DETAIL E
NOTES:
  1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
  2. CONTROLLING DIMENSION: MILLIMETER.
  3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
  4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
  5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
  6. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
−W−
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 2.90 3.10 0.114 0.122
B 2.90 3.10 0.114 0.122
C 0.80 1.10 0.031 0.043
D 0.05 0.15 0.002 0.006
F 0.40 0.70 0.016 0.028
G
0.65 BSC
0.026 BSC
K 0.25 0.40 0.010 0.016
L
4.90 BSC
0.193 BSC
M 0_ 6 _ 0_ 6_
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