MC100EPT24_16 Datasheet, PDF (1/8 Pages) ON Semiconductor – LVTTL/LVCMOS to Differential LVECL Translator

MC100EPT24
3.3 V LVTTL/LVCMOS to
Differential LVECL Translator
Description
The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL
translator. Because LVECL levels and LVTTL/LVCMOS levels are
used, a −3.3 V, +3.3 V and ground are required. The small outline
8-lead package and the single gate of the EPT24 makes it ideal for
those applications where space, performance, and low power are at a
premium.
Features
• 350 ps Typical Propagation Delay
• Maximum Input Clock Frequency = > 1.0 GHz Typical
• The 100 Series Contains Temperature Compensation
• Operating Range:
V_CC = 3.0 V to 3.6 V; V_EE = −3.6 V to −3.0 V; GND = 0 V
• PNP LVTTL Input for Minimal Loading
• Q Output will Default HIGH with Input Open
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
www.onsemi.com
8
1
8
1
SOIC−8 NB
TSSOP−8
DFN8
D SUFFIX
DT SUFFIX MN SUFFIX
CASE 751−07 CASE 948R−02 CASE 506AA
MARKING DIAGRAMS*
8
KPT24
ALYW
G
1
SOIC−8 NB
8
KA24
ALYWG
G
1
TSSOP−8
14
DFN8
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
M
= Date Code
G
= Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
Package Shipping†
MC100EPT24DG
SOIC−8 NB 98 Units / Tube
(Pb-Free)
MC100EPT24DR2G
SOIC−8 NB 2500 Tape & Reel
(Pb-Free)
MC100EPT24DTG
TSSOP−8
(Pb-Free)
100 Units / Tube
MC100EPT24MNR4G
DFN8
1000 Tape & Reel
(Pb-Free)
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
1
August, 2016 − Rev. 10
Publication Order Number:
MC100EPT24/D