CM1235_14 Datasheet, PDF (7/9 Pages) ON Semiconductor – Small Footprint ESD Clamp Array for High Speed Data Line Protection

CM1235
100.0 W
Figure 8. Typical Channel TDR Measured Across Out_x and In_x Per Each
Differential Channels Pair (Typical 200 ps Incident Rise Time)
Application Information
CM1235 Application and Guidelines
As a general rule, the CM1235 ESD protection array should be located as close as possible to the point of entry of expected
electrostatic discharges with minimum PCB trace lengths to the ground planes and between the signal input and the ESD device
to minimize stray series inductance.
Figure 9. Application of Positive ESD Pulse
Between Input Channel and Ground
Additional Information
See also ON Semiconductor Application Note “Design
Considerations for ESD Protection,” in the Applications
section at www.onsemi.com.
Figure 10. Typical PCB Layout
http://onsemi.com
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