CAT93C66 Datasheet, PDF (7/17 Pages) ON Semiconductor – 4-Kb Microwire Serial CMOS EEPROM

CAT93C66
Write
After receiving a WRITE command (Figure 4), address
and the data, the CS (Chip Select) pin must be
deselected for a minimum of t_CSMIN. The falling edge of
CS will start the self clocking clear and data store cycle
of the memory location specified in the instruction. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the CAT93C66 can be determined by
selecting the device and polling the DO pin. Since this
device features Auto-Clear before write, it is NOT
necessary to erase a memory location before it is
written into.
Erase
Upon receiving an ERASE command and address,
the CS (Chip Select) pin must be deasserted for a
minimum of t_CSMIN (Figure 5). The falling edge of CS
will start the self clocking clear cycle of the selected
memory location. The clocking of the SK pin is not
necessary after the device has entered the self
clocking mode. The ready/ busy status of the
CAT93C66 can be determined by selecting the device
and polling the DO pin. Once cleared, the content of a
cleared location returns to a logical “1” state.
Figure 3. EWEN/EWDS Instruction Timing
SK
CS
STANDBY
DI
1
00
*
* ENABLE = 11
DISABLE = 00
Figure 4. Write Instruction Timing
SK
CS
AN AN-1
DI
101
A0 DN
HIGH-Z
DO
Figure 5. Erase Instruction Timing
SK
tCSMIN
STATUS
VERIFY
D0
STANDBY
tSV
BUSY
READY
tEW
tHZ
HIGH-Z
CS
AN AN-1
A0
DI
11
1
STATUS VERIFY
tCS
STANDBY
tSV
tHZ
HIGH-Z
DO
BUSY READY
HIGH-Z
tEW
© 2009 SCILLC. All rights reserved
7
Characteristics subject to change without notice
Doc. No. MD-1089 Rev. T